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| hackerfoo | Where is the analysis implemented? Is it in ABC? | 01:23 |
|---|---|---|
| hackerfoo | I've been working on bit-width inference for my compiler. | 01:28 |
| hackerfoo | You can try it here with `:bo 8` then `:bc gcd`: http://hackerfoo.com/eval.html | 01:29 |
| tpb | Title: popr (at hackerfoo.com) | 01:29 |
| hackerfoo | Some of the calculations are trivial, like addition, but others take a while to figure out: https://github.com/HackerFoo/poprc/blob/master/primitive.c#L378-L423 | 01:33 |
| tpb | Title: poprc/primitive.c at master · HackerFoo/poprc · GitHub (at github.com) | 01:33 |
| hackerfoo | There's a library, but I'd like to keep the code small: http://isl.gforge.inria.fr/ | 01:35 |
| tpb | Title: Index of / (at isl.gforge.inria.fr) | 01:35 |
| hackerfoo | I suppose I'll end up adding a simplex solver eventually. | 01:36 |
| hackerfoo | Oh, `:cv gcd` for Verilog, but it uses a lot of macros. | 01:38 |
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| pepijndevos | wen installing prjtrellis and compilin nextpnr I get ModuleNotFoundError: No module named 'database' | 14:05 |
| pepijndevos | I just followed https://github.com/SymbiFlow/prjtrellis#getting-started | 14:06 |
| tpb | Title: GitHub - SymbiFlow/prjtrellis: Documenting the Lattice ECP5 bit-stream format. (at github.com) | 14:06 |
| pepijndevos | guess I had to add -DTRELLIS_ROOT=/usr/share/trellis/ | 14:12 |
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| janrinze | does anyone know which standard is used for the two 'expansion' header connectors of the ecp5 evaluation board of lattice? I have been looking for boards that might fit on the connectors. | 14:45 |
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| ZipCPU | pepijndevos: Did you init submodules? Does the prjtrellis/database directory have anything in it? | 15:00 |
| ZipCPU | janrinze: Sorry, not me. | 15:01 |
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| janrinze | https://github.com/trabucayre/fixFT2232_ecp5evn anyone have experience with this solution? | 15:11 |
| tpb | Title: GitHub - trabucayre/fixFT2232_ecp5evn: Tool to fix FT2232s uart interface configuration for ecp5evn (LFE5UM5G-85F-EVN) board (at github.com) | 15:11 |
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| janrinze | daveshah: any chance if the packing density branch will improve the speed of the design? | 19:54 |
| daveshah | Unlikely | 20:02 |
| daveshah | It doesn't change anything until utilisation is around 95% | 20:02 |
| janrinze | daveshah: 95% utilisation on ecp5 is quite a design :D | 20:31 |
| daveshah | Well, that is slice utilisation with loose packing so can be hit quickly with designs with lots of FFs | 20:34 |
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| ZirconiumX | A LiteX SoC capable of running Linux can max out a -45F pretty easily | 20:48 |
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| daveshah | Only with Rocket - Vexriscv shouldn't be anywhere near that close | 21:03 |
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