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| promach | ERROR: timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc. | 01:27 |
|---|---|---|
| promach | yosys does not give me loop warnings | 01:27 |
| promach | so, what really causes this error ? | 01:27 |
| promach | ok, found what causes the error :) | 01:41 |
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| pepijndevos | How can I tell yosys not to do assign {foo, bar, baz} = {a, b, c}? | 11:03 |
| pepijndevos | I did splitnets but it still uses some arrays | 11:04 |
| pepijndevos | It's actually doing assign { gen_043_, gen_042_, gen_041_, gen_040_, gen_039_, gen_038_, gen_037_, gen_036_ } = { \ctr[25] , \ctr[24] , \ctr[23] , \ctr[22] , \ctr[21] , \ctr[20] , \ctr[19] , \ctr[18] }; | 11:05 |
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| ZirconiumX | pepijndevos: But why? This is, after all, entirely valid Verilog semantics | 11:19 |
| pepijndevos | ZirconiumX, but not Verilog that the Gowin floorplanner understands. | 11:20 |
| pepijndevos | It only deals with a very limited subset of post-synth Verilog | 11:20 |
| ZirconiumX | Hmm, write_verilog stuff like this might be one for whitequark? | 11:22 |
| daveshah | This is a known issue, see https://github.com/YosysHQ/yosys/issues/1286 | 11:23 |
| tpb | Title: Yosys emits assigns with a concatenated expression on the LHS · Issue #1286 · YosysHQ/yosys · GitHub (at github.com) | 11:23 |
| daveshah | Unfortunately structural Verilog isn't well defined | 11:23 |
| ZirconiumX | So yeah, have fun pepijndevos | 11:33 |
| ZirconiumX | :P | 11:33 |
| pepijndevos | I love fun | 11:35 |
| cr1901_modern | Issue #1286 came up in omigen... ISTR that this is _not_ valid Verilog | 12:02 |
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| daveshah | cr1901_modern: it definitely is | 12:28 |
| daveshah | see https://usercontent.irccloud-cdn.com/file/IiMjT1Jq/Screenshot%20from%202019-11-12%2012-28-00.png | 12:28 |
| daveshah | (from 1364-2005 p70) | 12:29 |
| daveshah | the question is whether it is "valid" structural Verilog, but I don't think structural Verilog is actually a defined thing | 12:29 |
| cr1901_modern | that's the sysverilog spec? | 12:31 |
| daveshah | No, Verilog 2005 | 12:31 |
| daveshah | I don't think it's a new feature | 12:31 |
| daveshah | let me check 01 | 12:31 |
| cr1901_modern | Okay, I'm wrong then. Well, ISE doesn't accept that either | 12:31 |
| daveshah | Yeah, same example appears in 2001 too | 12:32 |
| daveshah | I'm surprised by that, it's quite a common pattern | 12:32 |
| cr1901_modern | That being said, note that your example is {a, b} = c + d + e; | 12:34 |
| cr1901_modern | ISE doesn't accept {a, b} = {c, d}; | 12:34 |
| cr1901_modern | i.e. I think the destructuring on both sides is what it doesn't like | 12:34 |
| daveshah | That's even stranger | 12:34 |
| ZirconiumX | mwk: Why on earth did you decide to reverse engineer such a cursed compiler? | 12:35 |
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| FSM_Dude | Hey! Is there anyway here who develops/runs Yosys on a MacBook? | 12:51 |
| daveshah | It's definitely something some people do, don't think any of the core devs use macos though | 12:54 |
| FSM_Dude | Okay! I'm running into a problem since I updated Xcode / MacOS | 12:55 |
| FSM_Dude | I just ran make clean, and rebuilding everything to see if it might solve the issue | 12:55 |
| ZirconiumX | At risk of being snarky, it's difficult to help solve "problems" | 12:58 |
| FSM_Dude | I understand! I actually wanted to ask for help, then thought: maybe cleaning and rebuilding helps | 12:59 |
| ZirconiumX | Sure, but we still don't know what your problem is | 13:00 |
| FSM_Dude | If the problem persists, I'll let you guys know, and give a somewhat broader explanation what exactly goes wrong :) | 13:00 |
| FSM_Dude | Well, basically, when I ran fsm_recode -encoding binary, I get a Thread_Bad_Access | 13:01 |
| FSM_Dude | and then Yosys stops | 13:01 |
| ZirconiumX | This is already a lot more helpful | 13:01 |
| ZirconiumX | Can you post your code somewhere? | 13:02 |
| daveshah | If you don't get to the bottom of it quickly, running with valgrind (if that exists on osx) is often handy for this kind of thing | 13:02 |
| ZirconiumX | I think Valgrind has support for OS X | 13:02 |
| FSM_Dude | Cool, Ill look into it! | 13:05 |
| FSM_Dude | After rebuilding it still happens | 13:05 |
| FSM_Dude | I didn't change any code here | 13:06 |
| daveshah | It's possible that some latent bug has been triggered by a compiler/stdlib update | 13:06 |
| ZirconiumX | It wouldn't be the first bug we've had with fsm. | 13:08 |
| FSM_Dude | The Thread_Bad_Access seems to happen in register.cc | 13:10 |
| FSM_Dude | in Pass::call(RTLIL::Design *design, std::vector<std::string> args) | 13:10 |
| FSM_Dude | I'm fairly new to C++ and Yosys, so sorry for need being of great help... | 13:10 |
| ZirconiumX | Which line? | 13:10 |
| ZirconiumX | It'll say something like "register.cc:XXX" | 13:11 |
| mwk | ZirconiumX: well if it wasn't that cursed, I could perhaps actually use it instead of reversing it | 13:12 |
| ZirconiumX | ...You have a point | 13:12 |
| FSM_Dude | line number 294 : pass_register[args[0]]->execute(args, design); | 13:13 |
| FSM_Dude | For now I guess, Ill switch to my linux machine :P | 13:14 |
| mwk | FSM_Dude: could you give us the verilog / ilang code that triggers the bug? | 13:15 |
| FSM_Dude | Can I post it all here? | 13:16 |
| FSM_Dude | Or how do I get the Verilog to you guys | 13:16 |
| ZirconiumX | Copy and paste it to gist.github.com | 13:17 |
| ZirconiumX | Don't paste it into IRC; it will be very spammy and difficult to use | 13:17 |
| FSM_Dude | Okay | 13:17 |
| FSM_Dude | Mind you, it's not my verilog code. Im a student trying to run a set of verilog benchmarks. I'm interested in building new state encoding techniques into Yosys and analyse the outcomes | 13:20 |
| FSM_Dude | To analyse, I use a set of benchmark verilog files :) | 13:20 |
| ZirconiumX | Sure, but anything that takes in Verilog is inevitably going to crash somewhere | 13:22 |
| FSM_Dude | https://pastebin.com/xCKMfDKr | 13:22 |
| FSM_Dude | It's a shiftreg I think | 13:22 |
| FSM_Dude | I gtg now, Im on my laptop gonna get to my linux machine at home | 13:23 |
| ZirconiumX | ...It works under WSL | 13:24 |
| FSM_Dude | WSL? | 13:24 |
| ZirconiumX | Windows Subsystem for Linux | 13:24 |
| FSM_Dude | the fsm_recode -encoding binary? | 13:25 |
| ZirconiumX | Yep | 13:25 |
| FSM_Dude | Guess it's Xcode/OSx specific? | 13:25 |
| ZirconiumX | What's your full Yosys command line? | 13:25 |
| FSM_Dude | Thanks for testing tho! I'll switch to linux then | 13:25 |
| ZirconiumX | Sadly we can't fix the bug if you do | 13:25 |
| FSM_Dude | https://pastebin.com/3S1fGbi6 | 13:27 |
| FSM_Dude | Thats what I run | 13:27 |
| FSM_Dude | in the Yosys shell | 13:27 |
| ZirconiumX | That script works too | 13:30 |
| FSM_Dude | Hmm | 13:30 |
| FSM_Dude | Before I updated my OSx and Xcode everything worked. So I guess it has to do with that change | 13:30 |
| ZirconiumX | Possibly. That still suggests there's a latent bug *somewhere* | 13:30 |
| FSM_Dude | How can I investigate this better/be of help to you guys | 13:32 |
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| ZirconiumX | Funnily enough, Yosys has a command for finding bugs | 13:33 |
| ZirconiumX | So, I presume you have that script in a file somewhere? | 13:33 |
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| FSM_Dude | I type every command in the shell most of the times | 13:34 |
| ZirconiumX | You should put it in a script | 13:34 |
| ZirconiumX | And then use `yosys -s script.ys` | 13:34 |
| FSM_Dude | Okay, thanks! | 13:35 |
| ZirconiumX | Does that still crash with the segfault? | 13:35 |
| FSM_Dude | Yes | 13:37 |
| ZirconiumX | Right, so now I want you to run `yosys -p "bugpoint -clean -script script.ys; write_ilang testcase.il" your_verilog_file.v` | 13:39 |
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| FSM_Dude | autoidx 3 | 13:43 |
| FSM_Dude | is in both .il files | 13:43 |
| FSM_Dude | I gtg now, got classes. I'll come back to you! Let's try to fix it :) | 13:44 |
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