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| promach | Have anyone used https://github.com/FPGAwars/apio before ? | 08:24 |
|---|---|---|
| tpb | Title: GitHub - FPGAwars/apio: Open source ecosystem for open FPGA boards (at github.com) | 08:24 |
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| pepijndevos | welp Warning: Failed to find a route for arc 20 of net clk. | 08:25 |
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| whitequark | janrinze: yosys does not currently have TDP RAM support | 08:28 |
| whitequark | inference support* | 08:28 |
| pepijndevos | I probably have a typo or a missing pip somewhere, I think?? | 08:42 |
| pepijndevos | (using the generic backend to PnR stuff) | 08:42 |
| pepijndevos | It seems somehow that the clock wire doesn't have the right pips to connect all the way. | 08:42 |
| daveshah | There are some ifdefs in the router you can enable (combined with --debug) to see what it is trying | 08:48 |
| pepijndevos | Oh ok, I'll have a look | 08:49 |
| pepijndevos | Is there also a way to dump the internal routing graph? I suppose it might be a bit big to comprehend | 08:52 |
| daveshah | No, although in the past I've usually used python scripts to poke the routing graph | 08:53 |
| pepijndevos | daveshah, can you somehow get an interactive console into nextpnr, or you have to write the poking in --pre-pack over and over? | 09:04 |
| daveshah | the only interactive console is in the gui | 09:04 |
| daveshah | code.interact() in a script might also work | 09:06 |
| daveshah | But I haven't tried the latter | 09:06 |
| pepijndevos | Hm, does the gui work with generic? | 09:07 |
| pepijndevos | I tried good old pdb.set_trace() but that just hangs without getting a prompt | 09:08 |
| daveshah | Just tried and code.interact() seems to work | 09:08 |
| daveshah | Not sure about gui, I think there were some issues with the generic prepack scripts | 09:09 |
| pepijndevos | Where do you put that? NameError: name 'code' is not defined | 09:09 |
| daveshah | need an import code too | 09:09 |
| daveshah | something is needed for ctx to work properly too; let me see | 09:10 |
| daveshah | so these two lines are what you want | 09:11 |
| daveshah | import code | 09:11 |
| daveshah | code.interact(local=locals()) | 09:11 |
| pepijndevos | btw, this is the output with --debug, have not looked into it much further https://paste.ubuntu.com/p/K8mqCHr77J/ | 09:12 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 09:12 |
| daveshah | For routing graph debugging you probably want to uncomment some of the ifdefs in the router too to see what it visits along the way | 09:14 |
| pepijndevos | yea, will do that after I'm done poking at the Python api | 09:16 |
| promach | how do I create a pcf pins (clock and reset) declaration file for ice40 architecture ? | 09:32 |
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| daveshah | promach: have a look at https://github.com/YosysHQ/nextpnr/blob/master/docs/ice40.md | 09:39 |
| tpb | Title: nextpnr/ice40.md at master · YosysHQ/nextpnr · GitHub (at github.com) | 09:39 |
| daveshah | and examples like https://github.com/icebreaker-fpga/icebreaker-examples/blob/master/icebreaker.pcf | 09:39 |
| tpb | Title: icebreaker-examples/icebreaker.pcf at master · icebreaker-fpga/icebreaker-examples · GitHub (at github.com) | 09:39 |
| promach | thanks daveshah | 09:42 |
| pepijndevos | Yea, seems like there is no pip on the IOB output -.- | 09:46 |
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| daveshah | That would make sense | 09:49 |
| daveshah | It might be to do with IOLOGIC (input registers etc), needing to be routed through | 09:50 |
| pepijndevos | IIIINteresting... The IOB is connected to Q6, but a logic tile only has Q0-Q5 so my normal loop just doesn't make the right pip | 09:50 |
| daveshah | At a guess, non-logic interconnect tiles have the extra Q6-7 | 09:51 |
| daveshah | I wouldn't be surprised if things like BRAM needed those extra signals too | 09:51 |
| pepijndevos | Probably. But it also means the muxes just have different options at these locations. So I need to go back and figure that out. | 09:52 |
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| ZirconiumX | Can somebody poke Clifford? I sent him an email 4 days ago and I'm unsure if he got it | 11:05 |
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| * pepijndevos pokes | 11:11 | |
| ZirconiumX | Thanks Pepijn | 11:13 |
| pepijndevos | Although 4 days seems... not that much | 11:14 |
| pepijndevos | Maybe he'll see my poke in 4 days ;) | 11:15 |
| ZirconiumX | Sure, but email is rather opaque for this :P | 11:15 |
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| promach | Do anyone have pcf examples for tinyfpga similar to https://github.com/icebreaker-fpga/icebreaker-examples/blob/master/icebreaker.pcf ? | 11:53 |
| tpb | Title: icebreaker-examples/icebreaker.pcf at master · icebreaker-fpga/icebreaker-examples · GitHub (at github.com) | 11:53 |
| daveshah | promach: https://github.com/tinyfpga/TinyFPGA-BX/blob/master/icestorm_template/pins.pcf | 11:55 |
| tpb | Title: TinyFPGA-BX/pins.pcf at master · tinyfpga/TinyFPGA-BX · GitHub (at github.com) | 11:55 |
| promach | thanks daveshah | 11:56 |
| promach | ERROR: package does not have a pin named 'B2' (on line 94) ??? | 12:01 |
| promach | https://github.com/tinyfpga/TinyFPGA-BX/blob/master/icestorm_template/pins.pcf#L94 | 12:02 |
| tpb | Title: TinyFPGA-BX/pins.pcf at master · tinyfpga/TinyFPGA-BX · GitHub (at github.com) | 12:02 |
| daveshah | Are you passing --package to nextpnr | 12:02 |
| promach | what do you mean ? I am using GUI | 12:02 |
| daveshah | Are you choosing the right package? | 12:02 |
| promach | daveshah is it bg121 ? | 12:05 |
| daveshah | No, I think it is cm81 | 12:05 |
| promach | cm81 or cm81:4k ? | 12:06 |
| promach | for tinyfpga BX | 12:06 |
| daveshah | cm81 | 12:06 |
| promach | daveshah why is my json file https://github.com/promach/noc/blob/master/spidergon.ys#L9 is for hx1k ? | 12:08 |
| tpb | Title: noc/spidergon.ys at master · promach/noc · GitHub (at github.com) | 12:08 |
| daveshah | The json file doesn't contain a device | 12:08 |
| promach | once I open the JSON file, the GUI switch my choice from hx8k to hx1k | 12:09 |
| daveshah | I'm not sure why that is hapenning | 12:09 |
| promach | synth_ice40 -flatten -top NoC -json spidergon.json | 12:10 |
| promach | is this command correctly ? | 12:10 |
| daveshah | Yes | 12:10 |
| daveshah | It sounds like the problem is on the iCE40 side | 12:10 |
| promach | did I miss anything tinyfpga-specific parameters ? | 12:10 |
| daveshah | Try doing it on the command line nextpnr-ice40 --lp8k --json spidergon.json --package cm81 --gui | 12:11 |
| promach | you forgot pin.pcf | 12:11 |
| daveshah | oops | 12:11 |
| promach | daveshah usually which IO port is used for reset ? | 12:14 |
| promach | for tinyfpga BX ? | 12:14 |
| promach | https://github.com/tinyfpga/TinyFPGA-BX/blob/master/icestorm_template/pins.pcf | 12:14 |
| tpb | Title: TinyFPGA-BX/pins.pcf at master · tinyfpga/TinyFPGA-BX · GitHub (at github.com) | 12:14 |
| daveshah | Any of the pins | 12:14 |
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| promach | daveshah Warning: No clocks found in design | 12:57 |
| daveshah | Sounds like you don't have any registered timing paths | 12:58 |
| promach | I do not understand. I have so many always @(posedge clk) | 12:58 |
| daveshah | Are there flip flops in the synthesis statistics? | 12:58 |
| daveshah | they might be being optimised away | 12:58 |
| promach | daveshah is the no clock warning because of https://github.com/promach/noc/blob/master/spidergon.ys#L11 ? | 12:58 |
| tpb | Title: noc/spidergon.ys at master · promach/noc · GitHub (at github.com) | 12:58 |
| daveshah | No, because that doesn't remove any flops nor does it touch the JSON file that synth_ice40 previously created | 12:59 |
| promach | daveshah then what causes the no clock warning ? | 12:59 |
| daveshah | are there the right number (roughly) of SB_DFFs in the log output of synth_ice40 | 12:59 |
| promach | what log output ? | 13:00 |
| daveshah | it sounds a lot like your flipflops are being optimised out | 13:00 |
| daveshah | Yosys' log output | 13:00 |
| daveshah | It looks like your NoC module has only inputs | 13:00 |
| daveshah | That means all the remaining logic will be optimised away | 13:01 |
| promach | and ? | 13:01 |
| promach | you mean NoC.v | 13:02 |
| promach | ? | 13:02 |
| promach | daveshah | 13:02 |
| daveshah | yes | 13:02 |
| daveshah | that is your top module, right? | 13:02 |
| promach | yeah | 13:02 |
| promach | daveshah so, there is nothing wrong for "Warning: No clocks found in design" ? | 13:03 |
| promach | and I do not need to fix anything ? | 13:03 |
| daveshah | Well, your design is empty | 13:03 |
| promach | empty ? what do you mean ? | 13:03 |
| daveshah | There is no logic in your design | 13:03 |
| promach | ???? | 13:03 |
| promach | what ?! | 13:04 |
| daveshah | It's a circuit with only inputs | 13:04 |
| promach | so, the warning will go away once I add output ? | 13:04 |
| daveshah | Yes, because then there will be some logic left | 13:05 |
| daveshah | so long as that output depends on some clocked logic | 13:05 |
| promach | ok | 13:05 |
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| pepijndevos | I'm still messed up with DFF naming | 16:38 |
| pepijndevos | _DFFE_PP_ is positive clock, positive reset, right? | 16:38 |
| pepijndevos | I mean... positive enable | 16:38 |
| daveshah | positive clock, positive enable, no set/reset | 16:38 |
| pepijndevos | right | 16:38 |
| pepijndevos | __DFFS_PN0_ is positive clock negative reset, reset to zero? | 16:39 |
| daveshah | yes, active low sync reset to zero | 16:39 |
| pepijndevos | and __DFFNSE_PN0 is... is it now the reset or the enablet that is negative? | 16:40 |
| daveshah | reset | 16:41 |
| daveshah | negative enables aren't really well supported | 16:41 |
| daveshah | (dff2dffe doesn't map them, idk why there is even a primitive for them) | 16:41 |
| pepijndevos | So once you have a reset, negative enable is just not a thing | 16:41 |
| pepijndevos | Yea, that fixed it.. | 16:42 |
| pepijndevos | ty | 16:44 |
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