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| Xark | mrec: I believe it will work with Lattice tools, they are not super picky (default FT232H or FT2232H). | 04:22 |
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| mrec | which vendor/product id should the FT 2232 device have? | 11:50 |
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| mrec | ok the evb uses 6010 as productid | 11:55 |
| mrec | operation unsuccessful... what a shit this ftdi <-> ICE40 coupling | 12:18 |
| ZipCPU | mrec: Language, please | 12:51 |
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| mrec | can anyone recommend a chip adapter for the ice40up5? I think it's best to programm it before placing it. | 17:33 |
| daveshah | Probably best to see what Lattice have | 17:34 |
| daveshah | I presume you want to program nvcm then, that's quite specialised | 17:34 |
| mrec | I'm having too many problems with incircuit programming, I have a clock signal on MOSI or MISO... | 17:36 |
| mrec | so I guess something's connected inside the FPGA that should not be connected. | 17:37 |
| tnt | ?! | 17:39 |
| tnt | during programming the fpga is held in reset, it won't do anything. | 17:39 |
| whitequark | tnt: that is not the case | 17:40 |
| whitequark | while the FPGA is programmed, LEDs on glasgow blink for example | 17:40 |
| whitequark | i think that while the user logic is held in reset, the reconfiguring process itself can cause glitches | 17:41 |
| whitequark | on comb signals | 17:41 |
| tnt | But during configuration the IO ports should be disabled and held in their Z / weak-pull-up state. | 17:42 |
| mwk | huh, doesn't ice40 force-tristate all IOs? | 17:42 |
| tnt | I think they will switch between Z and weak-pull ups before the config is finished, but they should never be fully driven. | 17:44 |
| whitequark | ohhh | 17:47 |
| whitequark | yeah, that is probably what's happening then | 17:47 |
| mrec | the best for me would be if that chip would have a simple i2c interface for uploading the image... at least that could get me started with the rest of the board | 17:48 |
| daveshah | iCE40 SPI is simpler than I2C, tbh | 17:49 |
| mrec | not if you don't have an SPI interface on the rest of the board | 17:49 |
| mrec | https://github.com/icebreaker-fpga/icebreaker/blob/master/hardware/v1.0e/icebreaker-sch.pdf | 17:50 |
| tpb | Title: icebreaker/icebreaker-sch.pdf at master · icebreaker-fpga/icebreaker · GitHub (at github.com) | 17:50 |
| mrec | ADBUS3, ADBUS4 does anyone know what's used for temporary programming? | 17:50 |
| mrec | (I guess and hope it's adbus4) | 17:51 |
| mrec | well it's not working anyway. | 17:52 |
| tnt | You can't do SRAM programming the way the icebreaker is wired. | 17:52 |
| tnt | you can only program the flash | 17:52 |
| tnt | you need to swap the data line (miso/mosi) because the ftdi can't do that and you also need to make sure if you have a flash chip as well on there that its CS line will be disconnected from the fpga cs line. | 17:56 |
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| mrec | I just took it as reference for wiring up from the FTDI (which I have disconnected from an ICE40HX8K) | 17:58 |
| mrec | but there's still something wrong and it's not the swapped MOSI/MISO port | 17:59 |
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| mrec | is there any fool proof documentation out there which pins of the ftdi need a pull up and which don't for programming the ice40 part? | 19:06 |
| mrec | I'm only pulling up cdone and creset at the moment | 19:07 |
| cr1901_modern | I wonder how icestick permits SRAM programming by removing a single resistor if the lines have to be swapped too... | 19:10 |
| daveshah | Perhaps using bitbang rather than full MPSSE? | 19:12 |
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| tnt | mrec: TN1248 | 19:23 |
| tnt | cr1901_modern: where did you see that ? | 19:26 |
| mrec | I just found something... | 19:28 |
| mrec | need to re-wire the FTDI to my board | 19:28 |
| mrec | sclk and si are swapped hopefully that's it | 19:28 |
| mrec | it's already wrong in my schematic | 19:28 |
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| snajpa | has anyone tried building the LiteX ethernet soc for ECP5? https://github.com/enjoy-digital/versa_ecp5 | 19:38 |
| tpb | Title: GitHub - enjoy-digital/versa_ecp5: Versa ECP5 SoC based on LiteX (at github.com) | 19:38 |
| snajpa | I mean, recently enough | 19:39 |
| snajpa | Info: Max frequency for clock '$glbnet$eth_clocks0_rx': 103.91 MHz (FAIL at 125.00 MHz) | 19:39 |
| snajpa | I can't get above 118 MHz with prjtrellis | 19:39 |
| daveshah | Yes, this is a known issue, its always done this | 19:39 |
| snajpa | I see :) | 19:40 |
| snajpa | I've only seen the issue for the rmii_test | 19:40 |
| snajpa | *rgmii_test | 19:40 |
| daveshah | Yes, that's the one design that fails | 19:40 |
| daveshah | Doing the entire gigabit Ethernet stack with an 8 bit data path pushes an ECP5 a bit | 19:41 |
| snajpa | while :; do ./versa_ecp5.py ethernet --toolchain trellis && echo OK && break; done # no luck | 19:41 |
| daveshah | I've never seen it pass either | 19:42 |
| daveshah | It works fine | 19:42 |
| daveshah | The timing model Trellis uses is quite conservative anyway | 19:42 |
| snajpa | aha, so it does output the gateware? I didn't actually check | 19:42 |
| daveshah | No because the LiteX script stops | 19:43 |
| daveshah | Just rerun the ecppack line | 19:43 |
| snajpa | ok thanks a lot :) | 19:43 |
| mrec | well whatever I rewire not working of course seems like the up5k is not meant for me. | 20:29 |
| mrec | terrible chip | 20:29 |
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| snajpa | tftp booted, yay \o/ | 20:32 |
| snajpa | now all the new stuff, hook this up with SD emulator from Google Vault | 20:32 |
| snajpa | I wonder how does one simulate so complex designs - only short parts of the wave traces should be relevant... should be fun :) | 20:34 |
| mrec | what is that stupid device detection doing? just checking cdone or what? | 20:38 |
| daveshah | In what, iceprog? Yes | 20:42 |
| daveshah | It doesn't try and do any kind of ID read - I'm not even sure if iCE40s support such a thing | 20:42 |
| mrec | do you remember is there anything important that has to be taken care about when programming the sram? | 20:44 |
| mrec | I just can't figure out what's wrong with my setup | 20:44 |
| daveshah | No, the only thing I can think of is MOSI and MISO the wrong way round | 20:45 |
| daveshah | But in the worst case you can always try both options | 20:45 |
| daveshah | and just to check you are doing iceprog -S? | 20:45 |
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| mrec | VPP_2V5 is wired to 3V3 is that a problem? the datasheet says 3v3 is okay | 20:45 |
| mrec | I'm actually using the lattice windows tool | 20:46 |
| daveshah | 3V3 is fine | 20:46 |
| daveshah | Ah right | 20:46 |
| daveshah | That tends to be pretty unfussy about wiring too | 20:47 |
| daveshah | What's the exact error it gives? | 20:47 |
| mrec | it can't detect the device | 20:47 |
| cr1901_modern | tnt: I misremembered about icestick. "iceprog --help", one of the last paragraphs explains how to do sram programming w/ icestick | 20:48 |
| mrec | it detects the ftdi of course | 20:48 |
| daveshah | CRESET and SS are both connected? | 20:48 |
| tnt | mrec: are you sure it does SRAM programming ? | 20:48 |
| mrec | tnt: that's what I would like it to do | 20:49 |
| daveshah | I'm sure I've done SRAM programming with the Lattice tools once | 20:49 |
| daveshah | Indeed it's an official option on the dev kits too | 20:49 |
| mrec | creset and cdone are wired up | 20:50 |
| mrec | and pulled to 3v3 using 10k | 20:50 |
| tnt | which software are you using exactly ? | 20:51 |
| mrec | the windows programming tool that comes with radiant | 20:51 |
| mrec | is there any basic way to check if things are wired up correctly? | 20:52 |
| mrec | the chip is not getting hot :-) | 20:52 |
| tnt | Can you post screenshot of your configuration for the programmer ? | 20:53 |
| mrec | just saw that spi clock is supposed to have a pullup too | 20:54 |
| mrec | and ss_b | 20:55 |
| mrec | I'm just jumpwiring the ICE40HX evb | 20:55 |
| mrec | I desoldered the R0 resistors | 20:55 |
| mrec | which is R1-R6 I think | 20:55 |
| tnt | Radiant is for UP5k only ... does the programming sofware even work for a HX ?!? | 20:55 |
| mrec | the ice40hx evb is a ft2232 <-> ice40hx board, the ice40hx8k is disconnected | 20:56 |
| mrec | so I'm just using the ADBUSn connections of the ft2232 of that board | 20:57 |
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| mrec | ok I should just not assume that anything will be correct... | 21:22 |
| mrec | the FTDI is not pulling SSB to ground leaving the chip in SPI master mode | 21:22 |
| mrec | now the question is ... what needs to be fulfilled first .. cdone or ssb? | 21:26 |
| daveshah | I think that ssb needs to be low when *creset* is pulled low | 21:27 |
| daveshah | Or before it goes high again anyway | 21:27 |
| mrec | it's not even pulling creset low | 21:28 |
| daveshah | cdone is pulled low by the fpga, not by the programmer | 21:28 |
| mrec | cdone is low permanently | 21:28 |
| daveshah | That means the fpga isn't configured, as expected | 21:28 |
| daveshah | I would expect creset to be being pulled down and back high | 21:30 |
| daveshah | With ssb low by the time that creset goes high if not before, and ssb staying low while the programmer talks to the chip | 21:30 |
| mrec | it's definitely not getting pulled low | 21:33 |
| mrec | and it writes device detection failed... so the question is what is that firmware tool checking | 21:33 |
| daveshah | Is there any activity on any of the signals? | 21:34 |
| daveshah | Is it possible the wrong FTDI interface has been selected (B instead of A) - istr Diamond sometimes showed both | 21:34 |
| mrec | https://gojimmypi.blogspot.com/2018/05/FPGA-Programming-iCE40UP5K-B-EVN.html | 21:35 |
| tpb | Title: GoJimmyPi: Programming the Lattice Semiconductor FPGA iCE40 Ultra Plus Breakout Board iCE40UP5K-B-EVN (at gojimmypi.blogspot.com) | 21:35 |
| mrec | In the end I was eventually successful, but I don't think the iCE40UP5K is for everyone. | 21:35 |
| mrec | :-) | 21:35 |
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| mrec | FTUSB-1 is triggering a reset | 21:37 |
| mrec | FTUSB-0 is not | 21:37 |
| mrec | ok back to rewiring | 21:37 |
| mrec | that's it | 21:44 |
| mrec | it works now... | 21:44 |
| mrec | thought the HW is the problem while the software setting was it somewhat thanks for the reset hint | 21:45 |
| mrec | I cannot remember that I have ever set the port to FTUSB-1 when uploading the configuration | 21:45 |
| mrec | suddenly it's needed | 21:45 |
| mrec | guess if I would have gone with the linux tool it would have worked from the beginning on ... | 21:46 |
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