Monday, 2019-09-23

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ZirconiumXdaveshah: So, I've been trying to bugpoint a FlowMap crash, but while the original Verilog source works, exporting it to RTLIL and re-importing produces a "Module `model_fifo' is used with parameters but is not parametric!" error11:35
ZirconiumXWell, "works" as in "causes a FlowMap crash"11:35
daveshahWhat commands are you using?11:36
ZirconiumXTo dump RTLIL? Just `write_ilang`11:36
ZirconiumX(with a filename)11:36
daveshahWhat are you doing to it before writing? Might be worth trying a prep -flatten before writing11:38
daveshahOr at least hierarchy -top before writing if you don't want flattened rtlil11:38
ZirconiumXYeah, hierarchy -top prunes the erroring module, which is good enough11:39
ZirconiumXSince being able to prune modules means bugpoint converges faster, it should be a bit easier to work with?11:40
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rjohello! on ice40, is anyone using DYNAMICDELAY in the SB_PLL40_*? any code? any reports that it works? does changing DYNAMICDELAY require a RESETB pulse + wait for lock?16:01
rjoi have been playing with it for a while and can't seem to make any difference.16:02
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ZipCPUrjo: Hello!  Welcome to the channel!18:02
ZipCPUAlthough ... I'll admit, I haven't tried the DYNAMICDELAY on an iCE40 at all18:02
ZipCPUI'm also wondering currently if the similar primitive for the ECP5 does much ... but that's another story18:03
rjoWell. It doesn't do anything on ice40 because the parameter is ignored by nextpnr...18:23
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