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ZirconiumX | daveshah: So, I've been trying to bugpoint a FlowMap crash, but while the original Verilog source works, exporting it to RTLIL and re-importing produces a "Module `model_fifo' is used with parameters but is not parametric!" error | 11:35 |
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ZirconiumX | Well, "works" as in "causes a FlowMap crash" | 11:35 |
daveshah | What commands are you using? | 11:36 |
ZirconiumX | To dump RTLIL? Just `write_ilang` | 11:36 |
ZirconiumX | (with a filename) | 11:36 |
daveshah | What are you doing to it before writing? Might be worth trying a prep -flatten before writing | 11:38 |
daveshah | Or at least hierarchy -top before writing if you don't want flattened rtlil | 11:38 |
ZirconiumX | Yeah, hierarchy -top prunes the erroring module, which is good enough | 11:39 |
ZirconiumX | Since being able to prune modules means bugpoint converges faster, it should be a bit easier to work with? | 11:40 |
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rjo | hello! on ice40, is anyone using DYNAMICDELAY in the SB_PLL40_*? any code? any reports that it works? does changing DYNAMICDELAY require a RESETB pulse + wait for lock? | 16:01 |
rjo | i have been playing with it for a while and can't seem to make any difference. | 16:02 |
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ZipCPU | rjo: Hello! Welcome to the channel! | 18:02 |
ZipCPU | Although ... I'll admit, I haven't tried the DYNAMICDELAY on an iCE40 at all | 18:02 |
ZipCPU | I'm also wondering currently if the similar primitive for the ECP5 does much ... but that's another story | 18:03 |
rjo | Well. It doesn't do anything on ice40 because the parameter is ignored by nextpnr... | 18:23 |
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