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| FSM_Dude | Hey! Is this the right place to ask for help with Yosys? I'm using it for my studies, but I encounter some problem. | 11:33 |
|---|---|---|
| sorear | yes | 11:33 |
| FSM_Dude | Great! I already asked the question on SO, but did not have any luck with getting an answer there. I'm quite new to it, and I try to alter the FSM in the fsm_recode pass. If I do so, later on in the fsm_map pass yosys stops because an assertions is violated... | 11:36 |
| ZirconiumX | Which assertion? | 11:37 |
| sorear | https://stackoverflow.com/questions/57426951/yosys-how-to-correctly-add-states-and-transitions-to-fsm-during-fsm-recode-pass?r=SearchResults | 11:38 |
| tpb | Title: c++ - Yosys: How to correctly add states and transitions to fsm during fsm_recode pass? - Stack Overflow (at stackoverflow.com) | 11:38 |
| FSM_Dude | Yes, that one. | 11:38 |
| FSM_Dude | I managed to get rid of the assertion in a nasty way, but that only made thing worse. Once I ran abc and dfflibmap it showed me that there were 0 gates and 0 wires... | 11:40 |
| FSM_Dude | What Im trying to do, is add redundant states to the fsm. Afterwards I want to see the area of the design. This way I can compare the overhead generated by the added redundancy | 11:41 |
| ZirconiumX | You shouldn't need to hack into Yosys for it | 11:45 |
| ZirconiumX | AFAIK, it won't prune states that are used | 11:46 |
| ZirconiumX | So if you have a one-hot state and then add a wildcard state at the end which does something, I think it'll handle that reasonably efficiently | 11:47 |
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| FSM_Dude | I don't follow, sorry | 11:55 |
| pepijndevos | The symbiyosys docs mention only Z3 is mandatory, but say yices is the default prover... what's the deal there? | 12:02 |
| FSM_Dude | ZirconiumX, this https://imgur.com/a/NiVJafL is basically what I try to achieve within the fsm_recode pass of Yosys | 12:05 |
| tpb | Title: Imgur: The magic of the Internet (at imgur.com) | 12:05 |
| FSM_Dude | Would it be possible to add something like this to Yosys? Or is it impossible to alter the fsm within the c++ code? | 12:06 |
| pepijndevos | FSM_Dude, you're actually patching yosys to support a new type of FSM recoding? | 12:07 |
| FSM_Dude | I try to yes :) | 12:08 |
| FSM_Dude | I try to implement some fault tolerance into the FSM, and then analyse the overhead in terms of area etc | 12:09 |
| FSM_Dude | Just for my own research at uni | 12:10 |
| FSM_Dude | Now I'm wondering if it's even possible with Yosys lol | 12:10 |
| pepijndevos | That's super cool | 12:10 |
| daveshah | I expect the problem is the size of `state_onehot` is wrong | 12:11 |
| daveshah | You would need to look into where that is set, and perhaps resize it | 12:11 |
| FSM_Dude | daveshah, indeed. I think I need to resize some stuff. Also the fsm_data.copy_from_cell() function has some boundaries on the state_in and state_out of the transitions... | 12:13 |
| FSM_Dude | if (tr.state_in < 0 || tr.state_in >= state_num) tr.state_in = -1; if (tr.state_out < 0 || tr.state_out >= state_num) tr.state_out = -1; | 12:13 |
| FSM_Dude | Woops, sorry for that format... | 12:13 |
| daveshah | Yeah, I'm afraid I don't know the fsm stuff in Yosys well enough to help with the details | 12:14 |
| FSM_Dude | Hmm okay! Thanks for the tip tho! | 12:14 |
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| FSM_Dude | daveshah, that seemed to have fixed it :) | 12:45 |
| FSM_Dude | Now onto the next problem I face haha | 12:45 |
| FSM_Dude | Thanks a lot! | 12:45 |
| FSM_Dude | 27. Executing ABC pass (technology mapping using ABC).27.1. Extracting gate netlist of module `\test' to `<abc-temp-dir>/input.blif'..Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.Don't call ABC as there is nothing to map.Removing temp directory. | 12:47 |
| FSM_Dude | Guess I have a bigger problem than just the assertion lol | 12:47 |
| daveshah | `dump` and `show` are always helpful | 13:02 |
| pepijndevos | In my experience, when you connect something wrong, Yosys is more than happy to optimize away the disconnected logic haha | 13:03 |
| FSM_Dude | Thanks Im gonna have a look! | 13:08 |
| FSM_Dude | pepijndevos Hopefully my redundant states wont be optimized away... :P | 13:09 |
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| cr1901_modern | It is a rite of passage to play a fun game of "guess why the FPGA synthesizer optimized away my whole design" | 13:28 |
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| GenTooMan | cr1901_modern I am glad I got that out of my system several weeks ago I suppose. | 20:41 |
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| daveshah | It shows how easy it is to determine a lack of side effects in hardware, tbh | 20:45 |
| daveshah | Software compilers tend to be much less keen/able to optimise large chunks of code away | 20:45 |
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