| *** tpb has joined #yosys | 00:00 | |
| *** tpb has joined #yosys | 00:20 | |
| *** emeb_mac has quit IRC | 02:13 | |
| *** X-Scale` has joined #yosys | 02:36 | |
| *** X-Scale has quit IRC | 02:37 | |
| *** X-Scale` is now known as X-Scale | 02:37 | |
| *** emeb_mac has joined #yosys | 03:01 | |
| *** PyroPeter has quit IRC | 03:12 | |
| *** citypw has joined #yosys | 03:20 | |
| *** PyroPeter has joined #yosys | 03:25 | |
| *** futarisIRCcloud has joined #yosys | 04:54 | |
| *** AlexDaniel has joined #yosys | 04:54 | |
| *** Jybz has joined #yosys | 04:54 | |
| *** AlexDaniel has quit IRC | 04:58 | |
| *** AlexDaniel has joined #yosys | 04:58 | |
| *** AlexDaniel has quit IRC | 05:16 | |
| *** rohitksingh has joined #yosys | 05:22 | |
| *** rohitksingh has quit IRC | 05:31 | |
| *** rohitksingh has joined #yosys | 05:48 | |
| *** AlexDaniel has joined #yosys | 06:02 | |
| *** pepijndevos has quit IRC | 06:09 | |
| *** pepijndevos has joined #yosys | 06:12 | |
| *** AlexDaniel has quit IRC | 06:18 | |
| *** AlexDaniel has joined #yosys | 06:31 | |
| *** jakobwenzel has quit IRC | 06:36 | |
| *** jakobwenzel has joined #yosys | 06:37 | |
| *** AlexDaniel has quit IRC | 06:52 | |
| *** AlexDaniel has joined #yosys | 06:52 | |
| *** gmc has quit IRC | 06:57 | |
| *** gmc has joined #yosys | 06:59 | |
| *** emeb_mac has quit IRC | 07:13 | |
| *** rohitksingh has quit IRC | 07:51 | |
| *** elGamal has quit IRC | 08:08 | |
| *** elfGamal has joined #yosys | 08:08 | |
| *** AlexDaniel has quit IRC | 08:11 | |
| *** AlexDaniel has joined #yosys | 08:23 | |
| *** pie_ has quit IRC | 08:24 | |
| *** AlexDaniel has quit IRC | 08:29 | |
| *** dys has quit IRC | 08:42 | |
| *** elfGamal has quit IRC | 08:42 | |
| *** elGamal has joined #yosys | 08:42 | |
| *** Jybz has quit IRC | 09:07 | |
| *** Jybz has joined #yosys | 09:07 | |
| *** rohitksingh has joined #yosys | 09:24 | |
| *** AlexDaniel has joined #yosys | 09:40 | |
| *** AlexDaniel has quit IRC | 09:45 | |
| *** citypw has quit IRC | 10:14 | |
| *** wifasoi has joined #yosys | 10:36 | |
| *** dys has joined #yosys | 10:56 | |
| *** wifasoi has quit IRC | 11:18 | |
| *** pie_ has joined #yosys | 11:29 | |
| *** adjtm has quit IRC | 12:19 | |
| pepijndevos | Can Yosys (not nextpnr) give me my critical path? | 12:55 |
|---|---|---|
| pepijndevos | Or alternatively, how hard would it be to use the generic target for 74xx? | 12:55 |
| tnt | yosys has no timing analysis or timing data | 12:56 |
| pepijndevos | Not even a simple unit delay something to synthesize for speed? | 12:59 |
| tnt | not that I know | 12:59 |
| tnt | it's not timing driven synthesis at all. | 12:59 |
| daveshah | ABC uses this stuff internally | 12:59 |
| pepijndevos | Ah I see | 13:00 |
| daveshah | ABC does do timing driven synthesis, using delay info from liberty files (for ASIC), unit delays (for `abc` LUT synthesis) or box/lut files (for `abc9` LUT synthesis) | 13:00 |
| tnt | daveshah: really ? It optimize for depth ? | 13:00 |
| daveshah | Yes | 13:00 |
| daveshah | However, `abc` doesn't count boxes (e.g. carries) in depth - but `abc9` does | 13:01 |
| pepijndevos | (what's the diff between abc9 and abc?) | 13:01 |
| daveshah | abc9 uses newer commands in abc that are capable of handling whiteboxes | 13:01 |
| pepijndevos | But abc9 only does LUT, right? | 13:01 |
| daveshah | and uses a different format (xaig rather than blif) to better represent these whiteboxes | 13:01 |
| daveshah | Yes, right now anyway | 13:01 |
| pepijndevos | So can I extract this timing stuff from abc, or would it be easier to somehow use the generic nextpnr? | 13:03 |
| daveshah | You probably won't get much of use from abc | 13:03 |
| pepijndevos | Right now 74xx liberty has no real timing info, but I want to get a rough idea of the maximum frequency of my 74xx CPU :) | 13:03 |
| daveshah | tbh topological timing analysis is sufficiently simple I'd just hack something together than trying to do it in nextpnr | 13:04 |
| pepijndevos | Right... just export to json and hack up some python | 13:04 |
| daveshah | just toposort all your combinational cells and walk forward determining max delay | 13:04 |
| daveshah | yup | 13:04 |
| pepijndevos | topsort?? | 13:04 |
| daveshah | https://en.wikipedia.org/wiki/Topological_sorting | 13:05 |
| tpb | Title: Topological sorting - Wikipedia (at en.wikipedia.org) | 13:05 |
| *** indy has quit IRC | 13:06 | |
| daveshah | Incidentally, the long term (end of the year at the earliest) plan is to represent timing information inside Yosys using `specify`blocks in the Verilog cell white/blackbox libraries | 13:06 |
| ZipCPU | davehah: Really? Wow. I like it, but I am a bit surprised by the decision | 13:07 |
| ZipCPU | pepijndevos: If you are interested in critical path timing information from Yosys today, consider the LTP command. It's not quite what you want, but it is related | 13:08 |
| ZipCPU | LTP = Longest topological path | 13:08 |
| pepijndevos | oh!! | 13:08 |
| *** pie_ has quit IRC | 13:08 | |
| ZipCPU | Don't forget to exclude FF's, since they aren't typically part of any actual timing chain | 13:09 |
| pepijndevos | Will -noff still work after techmapping? | 13:09 |
| ZipCPU | Not likely, but there are ways to still get it to work | 13:10 |
| ZipCPU | (If I remember them) | 13:10 |
| ZipCPU | Let's see ... it was something like "ltp t:*FF* %n" IIRC, where you can replace *FF* with whatever you are using for FFs | 13:11 |
| pepijndevos | That seems to work! But... the signal names are all like $abc$1375$auto$ghdl.cc:290:import_module$47[15] so a bit hard to tell what it means | 13:17 |
| ZipCPU | Yeah, exactly | 13:18 |
| ZipCPU | So ... | 13:18 |
| ZipCPU | I talked with clifford about this, and got him to name both inputs and outputs of a FF with the name of the FF (usually found w/in the design) | 13:18 |
| ZipCPU | Check for the first and last element in the LTP string, and that should help | 13:19 |
| ZipCPU | You can also use "show" to figure out what's going on, perhaps even increasing the size of the incoming cone with something like "%ci1" or some such | 13:19 |
| pepijndevos | The string I pasted was the last one... the first one is just a human-named signal | 13:20 |
| pepijndevos | Show is not a bad idea | 13:20 |
| pepijndevos | What's that bit about the incomming cone? | 13:20 |
| ZipCPU | The incoming cone shows all the logic incoming to the currently seleected set of elements. IIRC, %ci1 shows adds all the inputs to the current selection to the selection, %ci2 adds the inputs to those inputs and so on | 13:21 |
| ZipCPU | There's also an outgoing cone that might be useful, %co with the numbers having the same meaning. So you might consider adding %co1 to your LTP and see what happens | 13:22 |
| pepijndevos | oh, I can pass that to show you mean. Good idea... running show on the whole design.. takes a while. | 13:22 |
| ZipCPU | That should help if the result was just before a FF and the name was still incomprehensible | 13:22 |
| pepijndevos | Yay, %c02 actually shows the flip flop it goes to | 13:27 |
| pepijndevos | Can I somehow feed the output of ltp as the selection to show? | 13:28 |
| ZipCPU | Yes | 13:28 |
| ZipCPU | ... although I can't remember how to do it right now ... :/ | 13:29 |
| pepijndevos | lol | 13:29 |
| pepijndevos | Going over the help file it's not immediately obvious to me either. Maybe something with the select command? | 13:41 |
| pepijndevos | Looking at the source code I also don't see an obvious way to do it. | 13:44 |
| pepijndevos | Except of course parse the output of the command and then convert it to a selection with a hacky Python script. | 13:45 |
| *** adjtm has joined #yosys | 13:50 | |
| *** indy has joined #yosys | 13:54 | |
| *** rohitksingh has quit IRC | 14:10 | |
| pepijndevos | Lol, ok, I made a *very* hacky script to do it https://twitter.com/pepijndevos/status/1159108072222220289 | 14:34 |
| *** rohitksingh has joined #yosys | 14:37 | |
| *** emeb has joined #yosys | 14:53 | |
| *** somlo has quit IRC | 14:56 | |
| *** somlo has joined #yosys | 14:58 | |
| tnt | pepijndevos: how many chips is that cpu ? | 15:02 |
| pepijndevos | 82 last time I checked | 15:04 |
| tnt | Oh, that's reasonable. | 15:05 |
| pepijndevos | Hrmmmmmm right now the longest part of the critical path is the logic from the alu output to the register depending on the state and the opcode. | 15:12 |
| *** somlo has quit IRC | 15:26 | |
| pepijndevos | omg, according to my rough estimate my cpu should be able to run at 10MHz. All 74AC chips seem to have a worst case delay of 10ns, so with a critical path of 9 and a worst case set-up time of 5ns... | 15:35 |
| pepijndevos | Of course in my bit serial archt that's only 0.5MHz instructions per second... | 15:36 |
| pepijndevos | Typical propagation delays are more like 5ns, so 20MHz is not impossible... maybe | 15:38 |
| *** rohitksingh has quit IRC | 15:41 | |
| *** rohitksingh has joined #yosys | 15:57 | |
| *** citypw has joined #yosys | 16:05 | |
| *** somlo has joined #yosys | 16:11 | |
| *** citypw has quit IRC | 16:20 | |
| *** AlexDaniel has joined #yosys | 17:31 | |
| *** AlexDaniel has quit IRC | 17:35 | |
| *** pie_ has joined #yosys | 17:56 | |
| *** proteusdude has quit IRC | 18:17 | |
| *** proteusdude has joined #yosys | 18:21 | |
| *** adjtm has quit IRC | 18:23 | |
| *** Jybz has quit IRC | 19:21 | |
| *** adjtm has joined #yosys | 19:24 | |
| pepijndevos | How well are source attributs preserved through synthesis? You could make a script that reports how many gates a line of code produced | 19:25 |
| daveshah | Not very well - ABC's architecture means that input code and gates produced don't correlate in any meaningful way | 19:33 |
| *** rohitksingh has quit IRC | 19:42 | |
| *** elGamal has quit IRC | 19:47 | |
| *** rohitksingh has joined #yosys | 20:08 | |
| *** show has quit IRC | 20:29 | |
| *** show has joined #yosys | 20:36 | |
| *** dys has quit IRC | 20:43 | |
| *** rohitksingh has quit IRC | 20:44 | |
| ZirconiumX | Can somebody clarify the difference between $lcu and $alu? My understanding is that $alu is an adder/subtractor and a $lcu is a fast(ish) carry chain, but the line gets blurry when you need a carry chain for long additions | 20:46 |
| daveshah | `$alu` is usually the important one to map for FPGA things | 20:49 |
| bwidawsk | is yosys smart enough to use carry chains in FPGAs for connected arithmetic units? | 20:51 |
| daveshah | What do you mean for "connected arithmetic units"? | 20:51 |
| daveshah | btw, ZirconiumX, I just checked and nothing in Yosys should create a `$lcu` - but techmap will downmap a `$alu` to one | 20:52 |
| bwidawsk | output of adders in ALMs (or whatever the generic term for that is) | 20:52 |
| daveshah | Yes, stuff like + and - will become carry chains | 20:53 |
| daveshah | although this is more a function of the architecture techmap rules than Yosys itself | 20:53 |
| bwidawsk | well the attempt to use adjacent ALMs | 20:53 |
| bwidawsk | I suppose that is part of PNR | 20:53 |
| ZirconiumX | Should be PnR | 20:54 |
| *** emeb_mac has joined #yosys | 20:56 | |
| *** dys has joined #yosys | 20:58 | |
| *** emeb_mac has quit IRC | 21:10 | |
| *** s_frit has quit IRC | 21:35 | |
| *** elGamal has joined #yosys | 21:35 | |
| *** s_frit has joined #yosys | 21:36 | |
| *** AlexDaniel has joined #yosys | 21:38 | |
| *** AlexDaniel has quit IRC | 21:54 | |
| *** X-Scale` has joined #yosys | 22:14 | |
| *** X-Scale has quit IRC | 22:14 | |
| *** X-Scale` has quit IRC | 22:20 | |
| *** X-Scale has joined #yosys | 22:20 | |
| *** AlexDaniel has joined #yosys | 22:25 | |
| *** elGamal has quit IRC | 22:35 | |
| *** elGamal has joined #yosys | 22:41 | |
| *** adjtm_ has joined #yosys | 23:18 | |
| *** adjtm has quit IRC | 23:21 | |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!