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| pepijndevos | what are ANSI C style module declarations | 07:29 |
|---|---|---|
| tnt | pepijndevos: I think were you declare the module ports not inside the () of the module, but later. | 07:32 |
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| pepijndevos | ah I see. | 07:43 |
| pepijndevos | I never actually learned Verilog. To me it's just VHDL with C syntax and added WTF | 07:44 |
| sorear | …that’s the opposite of the distinction made in C | 07:44 |
| daveshah | Yeah, ANSI in Verilog is the same as C | 07:46 |
| daveshah | Everything in the module header | 07:46 |
| daveshah | With the "names in the module header, types below" style being non-ANSI | 07:46 |
| daveshah | https://www.hdlworks.com/hdl_corner/verilog_ref/items/PortDeclaration.htm | 07:48 |
| tpb | Title: Port Declaration (at www.hdlworks.com) | 07:48 |
| tnt | Oh ok. Then I always use ANSI style then. | 08:02 |
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| pepijndevos | Welp... voodoo ahoy | 12:43 |
| pepijndevos | When I simulate my cpu in ghdl with a vhdl testbench it works perfectly | 12:43 |
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| pepijndevos | When I read it with verific/ghdl and convert to verilog and run it in ikarus, I get all sorts of borkennes | 12:44 |
| pepijndevos | Interestingly, different types of brokenness if I synthesize first or not. | 12:45 |
| pepijndevos | Odly synthesized seems less broken than not. The direct verilog output is just straigt away xxxxxxx | 12:45 |
| tnt | Do you have an explicit reset ? | 12:46 |
| pepijndevos | Yyyyyes? I don't reset all the signals though, only the ones I care about. | 12:47 |
| tnt | And you're sure you haven't "forgotten" one ? :) | 12:48 |
| tnt | Although sometime the 'x' propagation is a little agressive and doesn't detect that a result will always be deterministic no matter what the input is. | 12:48 |
| pepijndevos | Ehhh, possible. I'll try if resetting all the things helps. | 12:49 |
| pepijndevos | But why is this only an issue when converting to verilog? | 12:49 |
| tnt | Else you need to actually look at the first 'x' that happens where it shouldn't and see why it's there. | 12:49 |
| pepijndevos | Yea I guess | 12:50 |
| tnt | pepijndevos: I have no idea how the conversion is done so I'm not sure if it's supposed to map to equivalent 'x' semantics or not ... | 12:50 |
| pepijndevos | hm ok | 12:50 |
| pepijndevos | Ah it seems not so happy about metavalues. Understandable. I thought I'd let the compiler do its thing and output some don't cares. | 13:33 |
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| pepijndevos | daveshah, I have an extremely weird issue, and could use some advice on ruling out a compiler bug if you have time. Basically my code breaks after doing techmap -map +/techmap.v; opt; but doing (n)one of the two is fine. | 14:34 |
| daveshah | pepijndevos: is this still involving x? | 14:34 |
| pepijndevos | nope | 14:34 |
| daveshah | anything else unusual? | 14:35 |
| pepijndevos | Well, it gives xxx after it optimizes away my design, but generally it's working without those two commands | 14:35 |
| daveshah | can you post the ilang before techmap/opt? | 14:35 |
| pepijndevos | Other than that the target is 74xx logic, not really :) | 14:35 |
| pepijndevos | yea, will do | 14:36 |
| pepijndevos | daveshah, https://paste.ubuntu.com/p/GS9KmpcGTx/ | 14:39 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 14:39 |
| daveshah | Out of curiosity, what is getting optimised away | 14:41 |
| pepijndevos | Hold on... some bits of the opcode... but at this point it's not actually broken yet... sorry, I was looking at the wrong thing to deretmine breakage | 14:44 |
| pepijndevos | So it's breaking at a later stage, brb | 14:44 |
| pepijndevos | ah, got it... more or less... it's something with muxes... will try to narrow it down | 14:46 |
| pepijndevos | But in that case it's probably simply a bug in our mux techmap... | 14:47 |
| pepijndevos | I would like to do something like equiv_opt techmap -map ../74_mux.v, but first it gives me warnings about not having SAT models for all the things, and then it gives a lot of unproven $equiv. What's a good way to test this techmap is correct? | 14:51 |
| daveshah | Simulation before and after mapping? | 14:52 |
| daveshah | Or loading in models for all cells | 14:52 |
| pepijndevos | What do you mean? | 14:53 |
| pepijndevos | Well, pretty much I know it is *not* correct | 14:54 |
| daveshah | Immediately before equiv_opt, do `read_verilog` or `read_liberty` *without* -lib (unlike in normal synthesis) to load in models | 14:54 |
| daveshah | Then simulation of a simple design (just a mux on its own) is probably your best bet | 14:54 |
| pepijndevos | Oh I see | 14:55 |
| daveshah | Just running synthesis of a mux on its own might be enough to highlight the problem | 14:55 |
| pepijndevos | Thanks, I'll give it a go :) | 14:56 |
| pepijndevos | Ehhh, I get that I can use whitebox models for my techmap, but it'll probably still complain about $_MUX8_ | 14:57 |
| pepijndevos | But I'll figure it out I think... | 14:58 |
| daveshah | If it's missing $_MUX8_ you could just give it this in a file: https://github.com/YosysHQ/yosys/blob/master/techlibs/common/simcells.v#L324-L332 | 15:00 |
| tpb | Title: yosys/simcells.v at master · YosysHQ/yosys · GitHub (at github.com) | 15:00 |
| pepijndevos | oh, sweet | 15:01 |
| daveshah | oops I mean https://github.com/YosysHQ/yosys/blob/master/techlibs/common/simcells.v#L287-L294 | 15:01 |
| tpb | Title: yosys/simcells.v at master · YosysHQ/yosys · GitHub (at github.com) | 15:01 |
| daveshah | of course | 15:01 |
| pepijndevos | jaaaaaaaaaaaa | 15:08 |
| pepijndevos | one misplaced ' in the liberty file later... | 15:08 |
| pepijndevos | no, I'm still an idiot... | 15:09 |
| pepijndevos | sigh | 15:09 |
| pepijndevos | cool Segmentation fault (core dumped) wat | 15:17 |
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| pepijndevos | I totally can't make it be happy about $_MUX4_ and still want to do the techmap | 16:16 |
| pepijndevos | I FOUND IT, I FOUND THE MISSING ' | 16:43 |
| pepijndevos | and a way to check equivalence that kinda worked... | 16:48 |
| pepijndevos | ZirconiumX, https://github.com/ZirconiumX/74xx-liberty/pull/17 phew, that was... something | 16:53 |
| tpb | Title: Make sure muxes are correct by pepijndevos · Pull Request #17 · ZirconiumX/74xx-liberty · GitHub (at github.com) | 16:53 |
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| ZirconiumX | pepijndevos: so one of the inputs wasn't correct? | 16:55 |
| pepijndevos | ZirconiumX, the MUX8 liberty model had a logic error. One of the dozen ' was in the wrong place | 16:58 |
| pepijndevos | At least now it's *proven* that it's equivalent to the simcell.v one | 16:58 |
| pepijndevos | So my CPU simulates correctly now in 74xx logic... that at least reduces the ways in which it can be wrong a bit. | 17:00 |
| pepijndevos | But it would not catch ABC using a cell correctly that's defined incorrectly. | 17:00 |
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