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| sorear | right, it’s not emulating a latch, it literally is one | 00:09 |
|---|---|---|
| sorear | it is synthesizing a latch from smaller components that are not themselves latches | 00:10 |
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| cr1901_modern | What does a latch from smaller components look like then (note that yosys has a $dlatch cell, so it wouldn't go the "back to back NAND gates" route)? | 00:13 |
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| sorear | I’d say a LUT programmed as a 2:1 mux, with the output fed back as one input | 00:31 |
| cr1901_modern | That seems reasonable to me too. I'm doing a few experiments where I modify an ilang input (that was created from a "real" Verilog latch) and see what cells yosys infers | 00:34 |
| cr1901_modern | One of them was a mux w/ feedback | 00:35 |
| cr1901_modern | I think | 00:35 |
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| maikmerten | hmmm... did something significant change within the last two weeks regarding yosys and nextpnr for the iCE40? My SoC went from ~2500 to ~3000 LCs, but f_max increased from ~35 MHz to ~40 MHz | 17:32 |
| maikmerten | so that's quite something | 17:33 |
| tnt | -relut was enabled by default yesterday. | 17:37 |
| tnt | but ... I wouldn't expect that from it. | 17:38 |
| maikmerten | ah, interesting | 17:39 |
| maikmerten | is there a description on what it does? | 17:41 |
| maikmerten | I'm invoking synthesis with "yosys -p 'synth_ice40; attrmvcp; write_json ./boards/hx8k-breakout/top.json'" | 17:42 |
| maikmerten | is there a simple way to disable relut for testing? | 17:42 |
| tnt | not really. I think the easiest is just to look at all the passes of synth_ice40 and call them manually and skip the unlut. | 17:43 |
| maikmerten | ewww. ;-) | 17:44 |
| maikmerten | I mean, the f_max is great, but I figure a noticable LC-increase was not anticipated? | 17:44 |
| tnt | https://github.com/YosysHQ/yosys/pull/1183/commits/b700a4b1c5dd086874c7024edb10674cf3c3a7c4 | 17:44 |
| tpb | Title: synth_ice40: switch -relut to be always on by whitequark · Pull Request #1183 · YosysHQ/yosys · GitHub (at github.com) | 17:44 |
| tnt | maikmerten: well, relut should yield a LUT decrease really ... | 17:45 |
| maikmerten | yeah, it does say merging and stuff | 17:45 |
| maikmerten | compiling https://github.com/YosysHQ/yosys/commit/a8c5f7f41ec0c829c29ae425b0074eb33fa2a30c (pre-enabling) to see if that makes a difference | 17:49 |
| tpb | Title: synth_ice40: fix help text typo. NFC. · YosysHQ/yosys@a8c5f7f · GitHub (at github.com) | 17:49 |
| maikmerten | yup, going back to that commit brings LC-count back to ~2500 | 18:00 |
| maikmerten | and f_max back to ~35 MHz | 18:01 |
| tnt | maikmerten: and if you do synth_ice40 -relut with that version you see the LC increase ? | 18:11 |
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| maikmerten | trying | 18:16 |
| maikmerten | tnt, https://paste.debian.net/1091495/ | 18:21 |
| tpb | Title: debian Pastezone (at paste.debian.net) | 18:21 |
| maikmerten | so relut *does* reduce the LC count | 18:21 |
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| maikmerten | but nextpnr doesn't pack things as tightly anymore | 18:21 |
| daveshah | Oh I think I know the problem | 18:22 |
| daveshah | The LUT map ordering changed to accommodate abc9 | 18:22 |
| daveshah | This will cause the relut changes to no longer allow the LUT and carry to be packed together | 18:22 |
| maikmerten | oh :-) | 18:23 |
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| tnt | daveshah: what do you mean by lut map ordering ? | 18:24 |
| daveshah | The $lut to SB_LUT port mapping | 18:25 |
| daveshah | https://github.com/YosysHQ/yosys/blob/master/techlibs/ice40/cells_map.v#L38 | 18:25 |
| tpb | Title: yosys/cells_map.v at master · YosysHQ/yosys · GitHub (at github.com) | 18:25 |
| daveshah | abc9 maps such that LUT input 0 should be the fastest | 18:25 |
| daveshah | But SB_LUT input 3 is the fastest | 18:25 |
| daveshah | afk right now, so can't look in detail | 18:25 |
| maikmerten | (is it useful if I provide my test case?) | 18:25 |
| maikmerten | (as in the .json files with and without relut, the Verilog stuff is MIT licenced anyway) | 18:26 |
| tnt | maikmerten: can you open an issue so this can get tracked ? | 18:27 |
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| maikmerten | sure | 18:27 |
| maikmerten | is this a nextpnr or yosys thing? | 18:27 |
| tnt | Ah well, this might be https://github.com/YosysHQ/yosys/issues/1187 already | 18:27 |
| tpb | Title: -relut appears to cause performance problems with ice40 synthesis · Issue #1187 · YosysHQ/yosys · GitHub (at github.com) | 18:27 |
| maikmerten | I suspect former | 18:27 |
| tnt | it's a yosys thing. | 18:28 |
| maikmerten | okay, I see a similar LC ballooning thing there | 18:28 |
| maikmerten | in my case, I at least get a wonderful f_max increase | 18:29 |
| tnt | Most likely your critical path was not an adder. But in picorv32 I know the critical path has a carry chain in it. | 18:30 |
| maikmerten | as far as I can tell my critical path is a subtraction, so there's a carry in there somewhere ;-) | 18:33 |
| maikmerten | https://paste.debian.net/1091514/ | 18:34 |
| tpb | Title: debian Pastezone (at paste.debian.net) | 18:34 |
| tnt | mmm, ok yeah, not all adders will be 'changed' by relut I guess. | 18:35 |
| maikmerten | (yeah, 33 bit subtraction for "less than unsigned" cpu_inst.alu_inst.ltu) | 18:35 |
| maikmerten | but the dramatic increase in f_max (veeeeeery nice) makes me wonder what it looked like before | 18:37 |
| tnt | maikmerten: https://pastebin.com/Uxc9HM5s | 18:38 |
| tpb | Title: diff --git a/techlibs/ice40/ice40_unlut.cc b/techlibs/ice40/ice40_unlut.cc index - Pastebin.com (at pastebin.com) | 18:38 |
| tnt | maikmerten: can you give that a shot ? | 18:38 |
| maikmerten | tnt, on yosys master? | 18:40 |
| tnt | maikmerten: you can apply it on what you're using now and just check with -relut option. | 18:44 |
| maikmerten | alright | 18:44 |
| maikmerten | tnt, sorry for my stupidity, but is this something "git am" should apply or is this a "raw" diff? | 18:48 |
| tnt | that's a raw diff | 18:49 |
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| maikmerten | patching file techlibs/ice40/ice40_unlut.cc | 18:54 |
| maikmerten | patching file techlibs/ice40/synth_ice40.cc | 18:54 |
| maikmerten | patch unexpectedly ends in middle of line | 18:54 |
| maikmerten | Hunk #1 FAILED at 344. | 18:54 |
| maikmerten | 1 out of 1 hunk FAILED -- saving rejects to file techlibs/ice40/synth_ice40.cc.rej | 18:54 |
| maikmerten | will manually replicate | 18:58 |
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| maikmerten | tnt, https://paste.debian.net/1091519/ | 19:05 |
| tpb | Title: debian Pastezone (at paste.debian.net) | 19:05 |
| maikmerten | that brings down LC usage compared to no relut | 19:06 |
| maikmerten | too bad f_max is back to normal ;-) | 19:07 |
| maikmerten | but one cannot have everything | 19:07 |
| maikmerten | (the subtraction carry chain is the critical path again) | 19:08 |
| tnt | maikmerten: did you try --placer heap ? | 19:08 |
| maikmerten | tnt, yup, it's my default placer | 19:09 |
| maikmerten | nextpnr-ice40 --randomize-seed --placer heap --hx8k --json top.json --pcf hx8k-breakout.pcf --asc top.asc --freq 28 | 19:09 |
| tnt | OTOH the fmax doesn't mean much because you ask for 12 MHz ... so it will stop even searching for anything better. | 19:09 |
| maikmerten | oh, in the past I didn't really an effect on f_max when asking for a higher frequency | 19:10 |
| maikmerten | but then again, I didn't try that in a while | 19:10 |
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| maikmerten | yeah, asking for 40 MHz (which appears to be attainable with yosys master by accident) doesn't really move things | 19:13 |
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| tnt | what soc is it btw ? | 19:23 |
| maikmerten | tnt, https://github.com/maikmerten/spu32 | 19:25 |
| tpb | Title: GitHub - maikmerten/spu32: Small Processing Unit 32: A compact RV32I CPU written in Verilog (at github.com) | 19:25 |
| maikmerten | tnt, it can do https://drive.google.com/file/d/1-6S2-pWhovTNroUEn83Zp2s6kCquv7ds/view?usp=sharing | 19:26 |
| tpb | Title: badapple.mp4 - Google Drive (at drive.google.com) | 19:26 |
| maikmerten | tnt, I'm using the HX8K breakout board, with some custom additions: https://drive.google.com/file/d/1-8XCHNu_fg2EPYMHQbVBrB6EDCN_Jlqu/view?usp=sharing | 19:27 |
| tpb | Title: IMG_20190623_211623362.jpg - Google Drive (at drive.google.com) | 19:27 |
| maikmerten | (I need to update that block diagram, the VGA unit is not text mode anymore) | 19:28 |
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