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| f003brv | just curious, has anyone ran into issues running iceprog on newer Macs? | 04:32 |
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| sorear | if someone had, you'd probably get a reply somewhere before asking for the fifth time | 04:34 |
| f003brv | kk this is why no one likes you | 04:37 |
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| pepijndevos_ | ZirconiumX, I tried adding the 74HC30 and it does not get used at all... even if I write out ~&counter | 11:05 |
| pepijndevos_ | But maybe I effed up the liberty logic. I just copied the 4-bit logic and extended it. I'm honestly not 100% sure if a multi-port NAND is all ANDS with a not in the end, or a tree of NANDs. | 11:09 |
| ZirconiumX | Hmmm... | 11:19 |
| daveshah | ABC often struggles to map gates with a large number of inputs, I think because of how it extracts gates in the netlist it becomes harder and harder to find a match | 11:21 |
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| daveshah | AIUI it would be a tree of ANDs with a not at the end | 11:21 |
| pepijndevos_ | In that case 4-bit NAND logic seems wrong? https://github.com/ZirconiumX/74xx-liberty/blob/master/74series.lib#L89 | 11:30 |
| tpb | Title: 74xx-liberty/74series.lib at master · ZirconiumX/74xx-liberty · GitHub (at github.com) | 11:30 |
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| pepijndevos_ | (same for 3) | 11:30 |
| ZirconiumX | It might be, | 11:30 |
| pepijndevos_ | The datasheet suggest something more exotic with NOR gates and inverters. huh https://assets.nexperia.com/documents/data-sheet/74HC_HCT20.pdf | 11:34 |
| pepijndevos_ | Ah, I guess it's that one identity where A+B=(A*B)' or something like that | 11:34 |
| pepijndevos_ | DeMorgan | 11:35 |
| pepijndevos_ | Yea, so if I'm not mistaken the inverters and nor is the same as an and gate, so daveshah is correct. Will make PR. | 11:37 |
| pepijndevos_ | Yosys did *not* like my attempt to explain it a JK flip-flop btw haha | 11:37 |
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| pepijndevos_ | What's the deal with pmux2shiftx and shregmap? Which one do I want for mapping to a 74xx shift register? | 13:50 |
| daveshah | If it is a fixed length shift register, you will want shregmap followed by a custom techmap rule | 13:55 |
| pepijndevos_ | Cool. | 13:55 |
| daveshah | For variable length shift registers, running pmux2shiftx first will allow a few more coding styles to be mapped but is not essential | 13:55 |
| pepijndevos_ | What is a pmux even hehe | 13:55 |
| daveshah | parallel mux | 13:56 |
| pepijndevos_ | But I think I want shregmap indeed | 13:56 |
| daveshah | pmux has one-hot (ish, anyway) select inputs | 13:56 |
| pepijndevos_ | "The generated shift register will be of type $__SHREG_DFF_[NP]_ and will use the same interface as the original $_DFF_*_ cells." | 13:57 |
| pepijndevos_ | Ehhhh, how does one SHREG have the same interface as a chain of DFF? In particular not 100% sure how it works with serial/parallel input. A chain of flip-flops would support parallel output, and maybe parallel input, right? | 14:00 |
| ZirconiumX | pepijndevos_: Because a SHREG (shift register) *is* a chain of DFFs | 14:01 |
| pepijndevos_ | sure sure, just in terms of verilog interface. | 14:02 |
| pepijndevos_ | https://github.com/YosysHQ/yosys/blob/6d74cf0d2b903eae16372f58dc15e4bc67666a2b/tests/various/shregmap.v#L15 from this is looks like you can really only set the input and get the output. https://github.com/YosysHQ/yosys/blob/6d74cf0d2b903eae16372f58dc15e4bc67666a2b/tests/various/shregmap.v#L15 | 14:04 |
| tpb | Title: yosys/shregmap.v at 6d74cf0d2b903eae16372f58dc15e4bc67666a2b · YosysHQ/yosys · GitHub (at github.com) | 14:04 |
| pepijndevos_ | dedp | 14:04 |
| daveshah | Most FPGA shift registers have one input and one or two outputs (some have a fixed and variable length output) | 14:05 |
| daveshah | You might be able to use the "tech" feature of shreg to add some custom mapping rules for sipo at least | 14:05 |
| tnt | Anyone knows what trying to call a task in a 'for' loop seems to not work at all ? Are you not supposed to do that ? (this is test-bench code) | 14:09 |
| pepijndevos_ | Hmmm, as far as I can tell you can only set it to xilinx or greenpack, or you mean patch yosys to support a tech 74xx option? XD | 14:09 |
| daveshah | Yes, patch yosys | 14:10 |
| pepijndevos_ | For counter extraction that goes both ways, yes, but for a very specific feature for a target that so far only 2 people care about, hmmm, let's just stick to fifo for now. | 14:13 |
| pepijndevos_ | I'll probably bug you about the counter pass later hehe | 14:14 |
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| pepijndevos_ | Seems the 74AC164 is the most common/available type | 14:41 |
| pepijndevos_ | How does the enable thing work in shregmap? | 15:14 |
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| pepijndevos_ | And uuuh, does it matter where in the process I run shregmap and the techpass? Seems I broke everything... | 15:18 |
| pepijndevos_ | Basically now I have mostly lower-case things at the end. | 15:19 |
| pepijndevos_ | Uhm, ok, fixed that, but not a single shift register is initiated. | 15:24 |
| daveshah | So you will want a general techmap first, then shregmap, then a techmap for shift registers | 15:29 |
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| pepijndevos_ | assign led = counter[0]; | 15:44 |
| pepijndevos_ | always @ (posedge clk) | 15:44 |
| pepijndevos_ | counter <= {1'b1, counter[7:1]}; | 15:44 |
| pepijndevos_ | Is that a reasonable shift register? | 15:44 |
| pepijndevos_ | Doing this after that tells me it converted no shift registers: | 15:45 |
| daveshah | I think so | 15:45 |
| pepijndevos_ | techmap -map +/techmap.v | 15:45 |
| pepijndevos_ | shregmap -maxlen 8 -clkpol pos | 15:45 |
| pepijndevos_ | techmap -map ../74_shreg.v | 15:45 |
| pepijndevos_ | Converted 0 dff cells into 0 shift registers. | 15:46 |
| daveshah | What is the full code? | 15:47 |
| daveshah | You might also need a opt_clean after the first techmap | 15:47 |
| pepijndevos_ | Hm, will try and then make a paste, or just commit all the broken stuff to a branch. | 15:48 |
| pepijndevos_ | no change | 15:48 |
| pepijndevos_ | DERPPPPPPP | 15:49 |
| pepijndevos_ | I had initialised the counter... | 15:50 |
| pepijndevos_ | Ok, so it works, but has very limited applications. Basically you can't do a parallel read/write or initialise/reset it. | 15:52 |
| pepijndevos_ | The chip has a global reset and enable, is there any way to expose that? | 15:52 |
| daveshah | The enable can be used with -enpol to shregmap | 15:53 |
| daveshah | Resets aren't supported as no FPGA shift register I know supports reset | 15:54 |
| pepijndevos_ | What if you do -match $_DFFSR? hehe | 15:57 |
| daveshah | It might work, but I wouldn't rely on it | 15:58 |
| daveshah | It's possible some nasty combinations like self resetting shift registers could missynthesise | 15:59 |
| pepijndevos_ | alright | 15:59 |
| pepijndevos_ | eh, I'm not even sure what code to write to make it want an enable. | 16:03 |
| pepijndevos_ | I thought I'd wrap the shift in an if, but that just make DFF with MUX | 16:05 |
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| daveshah | You probably need a dff2dffe to turn DFF with MUX into DFFE | 17:50 |
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| pepijndevos_ | daveshah, there are two of them already, even more? haha https://github.com/ZirconiumX/74xx-liberty/blob/master/synth_74.ys | 18:36 |
| tpb | Title: 74xx-liberty/synth_74.ys at master · ZirconiumX/74xx-liberty · GitHub (at github.com) | 18:36 |
| pepijndevos_ | eh, my version lives here: https://github.com/ZirconiumX/74xx-liberty/pull/12 | 18:37 |
| tpb | Title: Shift register pass by pepijndevos · Pull Request #12 · ZirconiumX/74xx-liberty · GitHub (at github.com) | 18:37 |
| pepijndevos_ | Oh wait, the second one undoes the dffe, why is that ZirconiumX? | 18:39 |
| pepijndevos_ | Ah I guess because our DFF are much more area efficient | 18:40 |
| pepijndevos_ | Eh.. 74377 seems fine to me. I mean it's half the pins of the 7416374, but it's also half the pins ;) (so chip count is worse, but area is about the same, except now with extra muxes) | 18:43 |
| daveshah | In any case you want to be running dff2dffe, particularly with unmap-min-ce, after doing a generic techmap run | 18:43 |
| pepijndevos_ | Why *with* unmap-mince? Doesn't that go back from dff to dff+mux? | 18:44 |
| daveshah | Yes, if ce is used less than a certain number of times | 18:46 |
| daveshah | Because each chip shares ce between 8 DFFs | 18:46 |
| daveshah | You probably want to do the unmap after mapping shift registers | 18:46 |
| pepijndevos_ | ah I see, so what it does is that if there are 5 DFFE with one clock enable, it'll not make a whole chip for that. | 18:48 |
| pepijndevos_ | Well, removing the mince made the shift register enable work. Althoug weirdly enouhg, it makes a NOT gate and a PP rather than a negative enable. Well, fine with me. Only thing I need to figure out is the correct order of things. | 19:07 |
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| pepijndevos_ | Eh... ZirconiumX as far as I can tell, the unmap-mince makes everything just worse. Saves about 700 chips total by removing it. | 19:19 |
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| pepijndevos_ | huh... why is there a lowercase $dff in my output... | 19:38 |
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