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| promach | have anyone experienced "loop warnings" yosys LTP command ? | 04:36 |
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| trmm | thanks, dave. the orpsoc example is very relevant since I'm trying to get the SDRAM on the ulx3s to work and that's exactly what the BIDIR pins are doing. | 12:35 |
| trmm | I'm a little uncertain about the clocking on the SDRAM -- it looks your orpsoc is using the system clock for the SDRAM, although my reading of the data sheet suggests that the SDRAM should be clocked with a 180-degree out of phase clock | 12:36 |
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| trmm | since the fpga is all positive edge clocked and the sdram is also positive edge clocked, it seems that this would cause the transitions to happen when the sdram expects the inputs to be stable. | 12:37 |
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| ovf | macro evaluation order seems to differ between yosys and icarus: http://vpaste.net/wQ2rg?raw . i don't have an opinion yet on which is correct or even why would anyone write code like this. | 22:23 |
| ZirconiumX | daveshah: Don't know if you're awake, but I found a Verilog module where I've got leaking $_DFF_PP[01]_ cells | 22:24 |
| daveshah | ZirconiumX: they would be flipflops with an async set or reset | 22:26 |
| ZirconiumX | So I need to find/define a cell that has those? | 22:27 |
| daveshah | Yes, once you do that dfflibmap should map them | 22:28 |
| daveshah | If you don't care about strict correctness, async2sync will turn them into soft logic and a normal DFF | 22:29 |
| daveshah | This will break any design relying on actual asynchronous behaviour though | 22:30 |
| ZirconiumX | I'm not entirely sure about how correct my existing designs are, though | 22:30 |
| ZirconiumX | Well | 22:30 |
| ZirconiumX | "design" | 22:30 |
| ZirconiumX | With `async2sync`, Yosys can turn a 6502 core into ~400 chips | 22:35 |
| daveshah | Incidentally, I think the default for abc is to optimise for delay rather than area | 22:38 |
| ZirconiumX | I did consider including delay information | 22:38 |
| daveshah | Passing -D 100000 to abc should cause it to optimise almost entirely for area instead | 22:38 |
| daveshah | or some other arbitrary big number | 22:38 |
| ZirconiumX | The AC family is a bit limited | 22:40 |
| ZirconiumX | Fast, but limited | 22:40 |
| ZirconiumX | daveshah: synthesis results appear to be identical for using -D 100000 versus not | 22:42 |
| ZirconiumX | Probably because I didn't add any delay information | 22:42 |
| daveshah | Yes, it might be optimising for area in any case then | 22:42 |
| ZirconiumX | I should probably add delay information, though, right? | 22:43 |
| daveshah | Yes, I'm not very familiar with the liberty format though | 22:44 |
| daveshah | I think you can even model things like drive strength and capacitance to get an idea of delay vs fanout | 22:44 |
| daveshah | Intended for ASIC cells but should have some relevance to discrete chips too... | 22:45 |
| ZirconiumX | One thing the 74151 has is an inverting output | 22:45 |
| ZirconiumX | I haven't looked into it much, but is there a way of telling Yosys "can you try doing an inverted mux too to see if that logic is easier?" | 22:46 |
| daveshah | No, not easily | 22:46 |
| bwidawsk | Has anyone done any work on documenting the quality differences on the generated bitstreams of diamond vs. yosys/nextpnr/trellis? | 22:46 |
| ZirconiumX | Failing that, can you pattern-match a mux followed by a not gate? | 22:47 |
| daveshah | ZirconiumX: there is the pmgen framework for building pattern matchers in Yosys | 22:47 |
| daveshah | But it's not that easy to use | 22:47 |
| daveshah | bwidawsk: I haven't done much experimentation, but usually yosys/nextpnr is about 30% behind | 22:48 |
| bwidawsk | in what, number of LEs used? | 22:48 |
| daveshah | Both number of LEs and Fmax | 22:49 |
| bwidawsk | daveshah› I'd really like to know how I can take those measurements myself, any help advice would be very much appreciated | 22:49 |
| bwidawsk | I'm happy to post what I find publicly | 22:49 |
| daveshah | Have a look at the log output for both, in particular the number of LUTs (after synthesis) of SLICEs (during pnr) | 22:50 |
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| daveshah | Timing is a bit harder particularly with Diamond you will need to search around a bit for the clock constraint that gives the best Fmax | 22:50 |
| bwidawsk | daveshah› is it scritable? | 22:50 |
| bwidawsk | scriptable | 22:50 |
| daveshah | nextpnr is, Diamond is a bit harder | 22:51 |
| bwidawsk | if you know off the top of your head what to grep, would you be so kind to share? If not, I can figure out | 22:51 |
| daveshah | You could probably look at this script https://github.com/SymbiFlow/prjtrellis/blob/master/diamond.sh for inspiration on how to script Diamond | 22:51 |
| tpb | Title: prjtrellis/diamond.sh at master · SymbiFlow/prjtrellis · GitHub (at github.com) | 22:51 |
| daveshah | I don't have anything readily available grep wise for Diamond though | 22:51 |
| daveshah | It should be fairly obvious. For timing you'll probably need to look at the twr timing report diamond generates | 22:52 |
| bwidawsk | k | 22:52 |
| bwidawsk | daveshah› thank you | 22:52 |
| bwidawsk | daveshah› oh, did your last statement imply you had something grepwise for yosys? | 22:53 |
| daveshah | It doesn't do area but https://github.com/YosysHQ/nextpnr-bench/blob/master/ice40/reports/report.py might help with runtime and Fmax | 22:54 |
| tpb | Title: nextpnr-bench/report.py at master · YosysHQ/nextpnr-bench · GitHub (at github.com) | 22:54 |
| bwidawsk | daveshah› thanks a bunch | 22:54 |
| daveshah | no problem | 22:55 |
| daveshah | Interested to see what the results are | 22:55 |
| bwidawsk | as a software person... I'm very ignorant, what's in between blicky, and like a risc-v core in terms of complexity? | 22:55 |
| bwidawsk | s/blicky/blinky | 22:55 |
| daveshah | Some of the smaller processor cores are quite interesting | 22:55 |
| daveshah | Like j1a, a forth processor | 22:56 |
| * bwidawsk nods | 22:56 | |
| bwidawsk | daveshah› do you happen to know if there is any hope of acheiving the same data with vivado, or quartus? I've looked at quartus and couldn't really get much out of it | 22:57 |
| bwidawsk | well, and I suppose much of the pipeline isn't done with open tools, as well | 22:57 |
| daveshah | Yes, definitely. But check the EULA because some tools don't allow public benchmarking (I think Diamond is fine) | 22:58 |
| daveshah | Both Vivado and Quartus have Tcl APIs that can be scripted | 22:58 |
| daveshah | There should be some examples out there of command line flows for both | 22:58 |
| bwidawsk | I just couldn't get quartus to dump much that seemed interesting, but I can't say I tried too hard | 22:58 |
| ZirconiumX | bwidawsk: I've been using a 6502 core which seems to be about halfway between the two | 22:59 |
| ZirconiumX | For even picorv32 | 22:59 |
| daveshah | At least in Vivado there are loads of report_ Tcl commands for this kind of thing | 22:59 |
| daveshah | e.g. report_utilization | 22:59 |
| bwidawsk | I'll take another look after I generate something with diamond, which seems more tractable given that you've actually done it :-) | 23:00 |
| bwidawsk | ZirconiumX› thanks | 23:00 |
| ZirconiumX | bwidawsk: https://github.com/Arlet/verilog-6502/ | 23:01 |
| tpb | Title: GitHub - Arlet/verilog-6502: A Verilog HDL model of the MOS 6502 CPU (at github.com) | 23:01 |
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