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| ZirconiumX | daveshah: (hi, yes, I'm back) Is the $lut cell always for constant values? | 19:14 |
|---|---|---|
| daveshah | ZirconiumX: yes, it is, although I'm not sure whether it appears unless you map to LUTs (either using `abc -lut` or some other method) | 19:26 |
| daveshah | `$shiftx` is usually used for both non-constant values, and also for LUT-style structures even with constant values following the frontend | 19:27 |
| ZirconiumX | I'm just wondering how best to utilise things like muxes | 19:27 |
| ZirconiumX | Since the 74 series has 16:1, 8:1, 4:1 and 2:1 muxes | 19:27 |
| ZirconiumX | abc seems to handle the 2:1 and 4:1 muxes | 19:28 |
| daveshah | You probably want to use the `pmux2shiftx` command shortly after initial optimisations (before synthesis), and then techmap suitable `$shiftx`s | 19:28 |
| daveshah | Eddie has been working on something like this for the Xilinx muxes | 19:29 |
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| daveshah | Actually, letting the default techmap rules map `$_MUX_` cells, then using `muxcover` to combine them to larger `$_MUX(4|8|16)_` cells, then techmapping those cells, is probably the path of least resistance | 19:33 |
| ZirconiumX | I need to use a proper Yosys script I think :P | 19:35 |
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| ZirconiumX | daveshah: Even just having muxcover alone is a major saving | 19:43 |
| ZirconiumX | Even if 25% of my gates are muxes now | 19:43 |
| ZirconiumX | Was 5,051 ICs, now 4,047 ICs | 19:44 |
| ZirconiumX | ...Mostly because the _MUXN_ cells weren't mapped | 19:45 |
| daveshah | Yes, you'll need techmap rules (albeit fairly simple ones) to turn them into the relevant 74xx | 19:46 |
| ZirconiumX | Presumably a MUX4 is a 4:1 mux? | 19:46 |
| daveshah | Yes | 19:46 |
| daveshah | See https://github.com/YosysHQ/yosys/blob/master/techlibs/common/simcells.v#L231-L313 | 19:47 |
| tpb | Title: yosys/simcells.v at master · YosysHQ/yosys · GitHub (at github.com) | 19:47 |
| tnt | When implementing a CPU in 74xx, usually you'd also use the OE of the various chips to drive/not-drive shared lines rather than using real muxes, not sure how yosys/abc maps that ? | 19:48 |
| daveshah | I'm pretty sure Yosys can only go in the other direction (from tristates to real muxes) | 19:49 |
| daveshah | using the `tribuf -logic` | 19:50 |
| ZirconiumX | daveshah: It's sort of like having an "& !OE" at the end of the output | 19:53 |
| ZirconiumX | tnt: I have fake tristate gates in my library | 19:55 |
| ZirconiumX | Essentially things like 7401s in wired-AND | 19:56 |
| ZirconiumX | Apparently ABC really like wired-AND NAND gates | 19:56 |
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| ZirconiumX | Though given that TI apparently don't make 7401s anymore, perhaps I should look for an alternative | 19:58 |
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| ZirconiumX | daveshah: Presumably replacing these _MUXN_ cells is a good time for _TECHMAP_REPLACE_? | 20:29 |
| daveshah | Yes | 20:30 |
| daveshah | That way the name of the _MUXN_ is preserved | 20:30 |
| ZirconiumX | So, we're now at 4,417 ICs | 20:38 |
| ZirconiumX | So that's a solid 10% reduction in chips | 20:38 |
| tnt | What's the target btw ? | 20:53 |
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| ZirconiumX | tnt: As in, target number of chips? | 21:01 |
| tnt | no, the target cpu you're trying to implement :) | 21:04 |
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| ZirconiumX | I wanted to design and build a (fairly small) RV32E CPU, but figured Yosys could probably do a better job than me if it knew how | 21:05 |
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| tnt | did you see http://www.halfbakedmaker.org/blog/lmarv1-1 ? | 21:07 |
| tpb | Title: Building LMARV-1: a tangible RISC-V processor, part 1 The Half-Baked Maker (at www.halfbakedmaker.org) | 21:07 |
| ZirconiumX | Yep | 21:10 |
| ZirconiumX | And a lot of the other ones | 21:10 |
| ZirconiumX | And they never got completed | 21:10 |
| ZirconiumX | Though to be fair I don't have particularly high hopes for this | 21:10 |
| ZirconiumX | We'll see | 21:10 |
| tnt | I think an hybrid approach might be the most viable. Design the "general architecture" manually, thing like registers, source/result bus ... and then use logic for the sub-units to automatically map to availbale logics. | 21:12 |
| tnt | just my 2ct. | 21:12 |
| tnt | Because tbh, 4000 chips seems ... big. | 21:12 |
| daveshah | I think you should be able to reduce the chip count quite a bit if you map RAM to a RAM chip rather than registers | 21:12 |
| daveshah | Might also be worth looking at SERV | 21:13 |
| tnt | https://en.wikipedia.org/wiki/74181 is nice but getting yosys to map it is going to be tricky for instance :p | 21:14 |
| tpb | Title: 74181 - Wikipedia (at en.wikipedia.org) | 21:14 |
| daveshah | If you have some kind of RAM available then SERV should need very little logic compared to picorv32, being bit serial | 21:14 |
| daveshah | Currently I'd imagine the register file dominates | 21:14 |
| ZirconiumX | Yeah, D-flip-flops make up 25% of the benchmark | 21:15 |
| ZirconiumX | 50%(!) is MUX4s | 21:15 |
| tnt | and how many of those mux4s have their inputs hardwired to 0/1 ? | 21:16 |
| tnt | (i.e. used at LUT2 :p) | 21:16 |
| ZirconiumX | I don't know how to check | 21:16 |
| daveshah | I imagine many of those MUX4s will be mixing DFFs | 21:16 |
| daveshah | *muxing | 21:16 |
| daveshah | You could try write_verilog and just look at the output | 21:17 |
| tnt | Ah yeah right, without shared busses / OE would be ... large in mux. | 21:17 |
| tnt | (and without ram) | 21:17 |
| ZirconiumX | So, there *are* SRAM chips, but they're fairly slow (fastest one I can find is 45ns response time) | 21:17 |
| daveshah | Yosys can only map RAM with separate read and write ports at the moment (and a lot of Verilog is written assuming this is available) | 21:19 |
| daveshah | Unfortunately this does limit mapping discrete RAM chips a bit | 21:19 |
| tnt | ZirconiumX: there are <=10ns sram. | 21:21 |
| ZirconiumX | tnt: Where? | 21:22 |
| ZirconiumX | Because the main discrete RAM chips I can find are the 62 series (e.g. the 62128 and 62256) | 21:23 |
| ZirconiumX | Which are 70ns DIP, but less if you use a smaller form factor | 21:23 |
| tnt | https://www.cypress.com/file/42721/download | 21:23 |
| tnt | (that's just a random one I picked) | 21:24 |
| ZirconiumX | tnt: Sure, but then you have to find chips which have separate read/write ports | 21:28 |
| tnt | You could double pump the SRAM. Or you can use a dural port sram. | 21:29 |
| tnt | https://www.idt.com/document/ovr/multi-port-memory-products-overview | 21:33 |
| ZirconiumX | I suppose it also goes against the spirit of building a CPU out of 74 series gates | 21:35 |
| ZirconiumX | If necessary I'll investigate it though | 21:35 |
| sorear | people totally used RAMs in the MSI era | 21:39 |
| ZirconiumX | Not saying they didn't | 21:39 |
| tnt | What's the widest D ff chip with OE ? | 21:40 |
| ZirconiumX | tnt: I *think* the 74A[H]C16373, which is technically tri-state | 21:45 |
| ZirconiumX | But there are 16 of them packed into a chip | 21:45 |
| tnt | That's actually a latch, not a ff | 21:47 |
| ZirconiumX | Then it'd have to be the 74x574 | 21:48 |
| ZirconiumX | tnt: Actually, how about the 16374? | 21:50 |
| tnt | Yeah, that would work. You'd need 128 of those for the register bank with two source bus output. | 21:51 |
| ZirconiumX | Okay, so that helps reduce the gate count a bit | 21:58 |
| ZirconiumX | I think I'll use chips from the AC family (which includes the '16374, but not the '150 MUX16) | 22:00 |
| ZirconiumX | daveshah: Can you get Yosys to turn a MUX16 into a pair of MUX8s and a MUX2? | 22:00 |
| ZirconiumX | (maybe change the muxcover costs?) | 22:00 |
| tnt | ZirconiumX: what voltage are you targetting btw ? 3v3 ? | 22:00 |
| ZirconiumX | 5V | 22:00 |
| ZirconiumX | I could consider 3V | 22:00 |
| ZirconiumX | *3V3 | 22:01 |
| daveshah | ZirconiumX: you can stop muxcover from inferring MUX16s at all | 22:01 |
| daveshah | Otherwise you could have the techmap rule for MUX16s create two MUX8s and a MUX2 | 22:01 |
| ZirconiumX | tnt: The problem is the distinct non-overlap between logic families | 22:02 |
| ZirconiumX | For example, the LVC family only has the 157 MUX2 | 22:03 |
| ZirconiumX | It is, however, very fast | 22:04 |
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