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promach | ZipCPU: not sure why yosys sby formal tool gave me that initial unknown thing. I will use iverilog and vivado simulator and solves most of the problems first | 02:51 |
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ZipCPU | Yeah, me neither--since the formal tools have never given me 'x's before | 02:52 |
ZipCPU | Are you sure you had -formal specified in your sby file? | 02:52 |
* ZipCPU is just making wild guesses at this point, having never seen this before | 02:52 | |
promach | ZipCPU: https://gist.github.com/promach/cf3ae626a85badad6cd822d3107c86b7#file-spidergon-sby | 02:56 |
tpb | Title: Spidergon Networks On Chip ยท GitHub (at gist.github.com) | 02:56 |
ZipCPU | Try using read_verilog -formal, and see if that makes any different from read_verilog -formal -sv | 03:02 |
promach | you mean without -sv ? | 03:03 |
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ZipCPU | Yes | 03:05 |
ZipCPU | It shouldn't make a difference since you don't have the sv license anyway | 03:06 |
ZipCPU | Although, you should know that the "read" command supercedes "read_verilog", but that discussion can wait for another day | 03:07 |
promach | I guess the issue lies somewhere else other than the sby file ;| | 03:07 |
promach | :| | 03:07 |
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ymherklotz | Hi, I would like to load a verilog design in yosys and append a string like "_1" to all the modules | 21:29 |
ymherklotz | using 'rename mod1 mod1_1' works, however, I saw that yosys has a -enumerate option | 21:30 |
ymherklotz | I can't seem to get it to work though, I have tried rename -enumerate A:* and selecting all the modules before calling rename -enumerate | 21:30 |
daveshah | As far as I know, -enumerate is intended to give things with dollar-prefixed internal names shorter names | 21:32 |
daveshah | It's not for renaming user modules | 21:32 |
ymherklotz | Ah ok, so it does not work on modules? | 21:32 |
daveshah | rename does, but -enumerate doesn't - it is for nets and cells with dollar prefixes (typically ones generated by Yosys) | 21:33 |
ymherklotz | Ah ok, is there another way I could batch rename modules? Or should I just stick to doing it individually? | 21:33 |
ymherklotz | I'm asking because I want to compare two designs that have the same module names in one top level module | 21:35 |
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daveshah | I think you have to do it individually | 21:36 |
ymherklotz | Great thanks! | 21:37 |
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