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| ZirconiumX | So I found a Yosys bug, and bisected it to git commit e158ea20, but don't know how to minimise Verilog (I'm new to HDL) | 14:54 |
|---|---|---|
| daveshah | Do you have any idea where the bug is happening? | 15:03 |
| ZirconiumX | Let me just submit my bug report | 15:04 |
| ZirconiumX | daveshah: https://github.com/YosysHQ/yosys/issues/981 | 15:04 |
| tpb | Title: Infinite loop while synthesizing for iCE40 · Issue #981 · YosysHQ/yosys · GitHub (at github.com) | 15:04 |
| daveshah | Thanks | 15:04 |
| ZirconiumX | An MCVE it is not, but I'm hoping it's a start | 15:05 |
| daveshah | These kinds of bugs tend to be alright to solve without minimal code (stuff like sim/synthesis mismatches are where minimal examples are really needed) | 15:06 |
| ZirconiumX | The git bisect commit looks odd to me; that's a logging commit | 15:09 |
| daveshah | Yeah that's what I'm trying to work out | 15:09 |
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| ZirconiumX | https://gist.github.com/ZirconiumX/4623903e14d1c5d735c391581b7e0dad | 15:12 |
| tpb | Title: bisect.txt · GitHub (at gist.github.com) | 15:12 |
| ZirconiumX | Here's the bisect log | 15:12 |
| ZirconiumX | daveshah: let me know if there's anything I can do | 15:13 |
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| alcorn | ^^ in answer to my previous question, here is how you can setup Yosys to be used as a library: https://pastebin.com/aJ12EXUz | 23:59 |
| tpb | Title: How to use Yosys as a library - Pastebin.com (at pastebin.com) | 23:59 |
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