| *** tpb has joined #yosys | 00:00 | |
| *** cr1901_modern has joined #yosys | 00:05 | |
| *** X-Scale has joined #yosys | 00:09 | |
| *** Cerpin has joined #yosys | 01:19 | |
| *** citypw has quit IRC | 01:23 | |
| *** citypw has joined #yosys | 01:24 | |
| *** futarisIRCcloud has joined #yosys | 01:52 | |
| *** PyroPeter has quit IRC | 02:27 | |
| *** emeb has quit IRC | 02:35 | |
| *** m_w has joined #yosys | 02:35 | |
| *** PyroPeter has joined #yosys | 02:40 | |
| *** Cerpin has quit IRC | 02:41 | |
| *** Cerpin has joined #yosys | 02:42 | |
| *** gsi__ has joined #yosys | 02:42 | |
| *** gsi_ has quit IRC | 02:46 | |
| *** m_w has quit IRC | 04:11 | |
| *** gsi__ is now known as gsi_ | 04:36 | |
| *** alcorn has joined #yosys | 04:37 | |
| *** rohitksingh has joined #yosys | 04:42 | |
| *** rohitksingh has quit IRC | 04:57 | |
| *** dys has quit IRC | 05:30 | |
| *** alcorn has quit IRC | 05:34 | |
| *** MoeIcenowy has quit IRC | 05:34 | |
| *** MoeIcenowy has joined #yosys | 05:35 | |
| *** rohitksingh has joined #yosys | 05:39 | |
| *** alcorn has joined #yosys | 05:44 | |
| *** alcorn has quit IRC | 05:49 | |
| *** emeb_mac has quit IRC | 06:33 | |
| *** ravenexp has joined #yosys | 06:43 | |
| *** Jybz has joined #yosys | 07:54 | |
| *** kraiskil has joined #yosys | 08:00 | |
| *** kraiskil has quit IRC | 08:13 | |
| *** GuzTech has joined #yosys | 08:16 | |
| *** kraiskil has joined #yosys | 08:34 | |
| *** kraiskil has quit IRC | 08:39 | |
| *** shenchen|zzz is now known as shenchen | 08:43 | |
| *** citypw has quit IRC | 08:56 | |
| *** citypw has joined #yosys | 09:16 | |
| *** dys has joined #yosys | 09:25 | |
| *** rohitksingh has quit IRC | 09:25 | |
| *** dys has quit IRC | 09:29 | |
| *** kraiskil has joined #yosys | 09:47 | |
| *** maikmerten has joined #yosys | 09:59 | |
| *** _whitelogger has quit IRC | 10:20 | |
| *** _whitelogger has joined #yosys | 10:22 | |
| *** dys has joined #yosys | 10:50 | |
| *** s_frit has joined #yosys | 10:56 | |
| *** futarisIRCcloud has quit IRC | 11:11 | |
| *** kraiskil has quit IRC | 11:33 | |
| *** kraiskil has joined #yosys | 13:10 | |
| *** emeb has joined #yosys | 14:20 | |
| *** kraiskil has quit IRC | 14:28 | |
| *** kraiskil has joined #yosys | 14:29 | |
| *** kraiskil has quit IRC | 14:51 | |
| *** GuzTech has quit IRC | 14:59 | |
| *** kraiskil has joined #yosys | 15:03 | |
| *** maikmerten has quit IRC | 15:13 | |
| *** kraiskil has quit IRC | 15:14 | |
| *** shenchen has quit IRC | 16:43 | |
| *** shenchen has joined #yosys | 17:00 | |
| *** Thorn has quit IRC | 17:03 | |
| *** Thorn has joined #yosys | 17:13 | |
| *** kraiskil has joined #yosys | 18:36 | |
| mithro | ZipCPU: You any good at understanding `select` commands? | 19:03 |
|---|---|---|
| ZipCPU | How so? | 19:03 |
| mithro | Actually, firstly - does Yosys have a `-Werror` type flag? | 19:04 |
| * ZipCPU looks up select commands | 19:04 | |
| *** adjtm has quit IRC | 19:04 | |
| ZipCPU | Not that I know of. I use verilator _Wall to as a lint checker | 19:05 |
| ZipCPU | Sorry, verilator -Wall -cc | 19:05 |
| mithro | I really want to turn this warning into an error -> Warning: wire '\o1' is assigned in a block at dff_two_clocks.sim.v:11. | 19:06 |
| mithro | ZipCPU: Because that actually seems to be the issue with my select commands... | 19:06 |
| ZipCPU | Are you familiar with that warning? | 19:07 |
| ZipCPU | That one was put into Yosys at my request | 19:07 |
| ZipCPU | It basically means that o1 was defined as a "wire" (not a "reg") and then assigned within an always @(*) block | 19:07 |
| ZipCPU | Verific catches these things and returns them as errors, so I thought Yosys should as well | 19:08 |
| ZipCPU | Internally, however, yosys doesn't really treat wires and reg's all that differently | 19:08 |
| ZipCPU | But ... at this point I'm probably not answering your question anymore ;) | 19:08 |
| emeb | ZipCPU: for most of my career I've been a Verilog coder. Then, about 8yrs ago I had to switch over to VHDL. This has made me appreciate languages that are much more strict. | 19:09 |
| daveshah | mithro: You can use -e regex to make a warning matching a regex into an error | 19:10 |
| emeb | Having to run my Verilog thru a few different tools which are persnickety about different things is annoying. I started using Verilator for linting a while back and this makes me happier. | 19:11 |
| mithro | daveshah: Oh? Where do I pass that? | 19:11 |
| daveshah | To the Yosys main command line | 19:11 |
| daveshah | There are a few other similar options that may be of interest too, see yosys -h | 19:11 |
| ZipCPU | emeb: o/ If there's one thing that annoys me, its verilog code that works fine with one parser from one vendor's tool, but not with another | 19:13 |
| emeb | ZipCPU: Just so. | 19:15 |
| mithro | yosys -e "wire '[^']*' is assigned in a block" | 19:21 |
| *** msgctl has quit IRC | 19:21 | |
| * ZipCPU scratches his head confused | 19:24 | |
| ZipCPU | daveshah? | 19:24 |
| daveshah | That looks correct to me | 19:24 |
| *** adjtm has joined #yosys | 19:25 | |
| *** rohitksingh has joined #yosys | 19:33 | |
| *** mirage335 has quit IRC | 20:01 | |
| *** rohitksingh has quit IRC | 20:10 | |
| *** rohitksingh has joined #yosys | 20:11 | |
| *** Jybz has quit IRC | 20:12 | |
| *** rohitksingh has quit IRC | 20:24 | |
| *** s_frit has quit IRC | 20:32 | |
| *** s_frit has joined #yosys | 20:33 | |
| *** kraiskil has quit IRC | 20:34 | |
| *** cr1901_modern has quit IRC | 20:54 | |
| *** dys has quit IRC | 21:33 | |
| *** dys has joined #yosys | 21:34 | |
| *** Cerpin has quit IRC | 21:35 | |
| *** Cerpin has joined #yosys | 21:57 | |
| *** mirage335 has joined #yosys | 22:00 | |
| *** MoeIcenowy has quit IRC | 22:13 | |
| *** MoeIcenowy has joined #yosys | 22:14 | |
| *** alcorn has joined #yosys | 22:24 | |
| *** sielicki has joined #yosys | 22:36 | |
| sielicki | One of my classes required us to write very backwards verilog at the beginning of the class, and now our class project is nearly complete and I'd like to remove some of the cruft that we had to use. | 22:38 |
| sielicki | https://github.com/cs-ece-552/assigns-sielicki/blob/synthesis/project/demo3/verilog/xnor5_1.v | 22:38 |
| tpb | Title: assigns-sielicki/xnor5_1.v at synthesis · cs-ece-552/assigns-sielicki · GitHub (at github.com) | 22:38 |
| sielicki | I want to propagate removal of just a set of these backwards / useless modules, across all modules. Not for any sort of synthesis reason but just for the sake of cleaning things up. I'm probably spending more time playing with yosys than it would take to just do it by hand, but I'm curious if anyone can help me figure out how to get my script in working order. | 22:40 |
| sielicki | Here's what I currently have: | 22:40 |
| sielicki | http://ix.io/1HN9 | 22:40 |
| sielicki | This is ultimately not what I want. Been pouring through the docs here for a bit. | 22:41 |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!