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| corecode | i'll have to look into that | 00:00 |
|---|---|---|
| corecode | but i do 4 layers anyhow | 00:00 |
| emeb_mac | unless you use tricks like tinyfpga does where he allows pads to short together & lose I/O count | 00:00 |
| corecode | uh no | 00:01 |
| corecode | no hax | 00:01 |
| corecode | i think it should be fine | 00:02 |
| corecode | if you break out diagonally | 00:03 |
| emeb_mac | they look like nice parts though - lots of resources. | 00:07 |
| corecode | so maybe i'm wrong | 00:10 |
| corecode | but 0.8mm ball pitch, that's 1.13mm diagonal | 00:11 |
| corecode | say 0.3mm land diameter, so that's 831um between lands | 00:11 |
| corecode | 0.2mm via drill + 120um anular ring = 391um left | 00:12 |
| corecode | which leaves 150um after 120um space | 00:12 |
| corecode | so plenty room | 00:13 |
| corecode | i might be missing something | 00:13 |
| cr1901_modern | >to init BRAM from a file <--- $readmemh? | 00:30 |
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| emeb_mac | corecode: yeah - a few years back I did the math on putting vias & traces between pads on BGAs and it was still feasible for 0.8mm pitch | 02:20 |
| emeb_mac | cr1901_modern: yes - that works for the complete build process starting from verilog. question was if it's possible to change BRAM contents *after* the bitstream has been built w/o redoing the whole synthesis/pnr/etc. | 02:22 |
| emeb_mac | would save some time for eg CPU code in BRAM ROMS | 02:23 |
| cr1901_modern | emeb_mac: Yes, use icebram for that | 02:26 |
| cr1901_modern | It is statistically extremely likely to work | 02:26 |
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| cr1901_modern | even though it relies on seeing a bitstream pattern that may or may not be valid outside of bram | 02:26 |
| emeb_mac | cr1901_modern: yep - will give it a try | 02:29 |
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