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| esden | tnt: has a photo of his bodge. | 00:00 |
|---|---|---|
| cr1901_modern | do not underestimate my ability to screw this up | 00:00 |
| esden | what you break you can fix ;) | 00:00 |
| cr1901_modern | how do I lift just 3 legs off the chip? | 00:00 |
| cr1901_modern | esden: ENOEXACTO for broken traces | 00:01 |
| esden | Kevin Hubbard aka. Black Mesa Labs: https://twitter.com/bml_khubbard | 00:01 |
| cr1901_modern | Ohhh right right | 00:01 |
| cr1901_modern | err, ENOXACTO* | 00:01 |
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| esden | Here we go... apropos: https://twitter.com/alexlomas/status/1102259891052445698?s=21 | 01:57 |
| sorear | there's a typo there right? | 02:01 |
| sorear | tweet says "6800" but the chips on the board are marked "68020" and "68882" (discrete FPU, fanschy) | 02:02 |
| sorear | has http://opencircuitdesign.com/pipermail/eda-dev/2019-February/000111.html been discussed here, or anywhere else I ought to join? | 02:12 |
| tpb | Title: [Eda-dev] 1st time silicon success on qflow! (at opencircuitdesign.com) | 02:12 |
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| emeb_mac | so that opencores osdvu UART I used in my icestick 6502 demo has some very weird stuff going on in it. | 04:25 |
| emeb_mac | in particular, the guts is all one synchronous process - blech. | 04:25 |
| emeb_mac | and to top it off, they used blocking assignments for everything. | 04:26 |
| emeb_mac | yosys mostly handled it OK, but there was one glitch where it crashed when I tried to use one of the outputs. I had to add some extra logic on the outside to make it work. | 04:27 |
| emeb_mac | during ABC step I'd get this: ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). | 04:34 |
| emeb_mac | and then within a few more lines of the output log it would throw an exception and crash | 04:34 |
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| emeb_mac | tnt: god help me - studying the cc65 docs to figure out how to make a custom target for this configuration. :P | 07:09 |
| tnt | edit https://github.com/cc65/cc65/blob/master/libsrc/Makefile :) | 07:13 |
| tpb | Title: cc65/Makefile at master · cc65/cc65 · GitHub (at github.com) | 07:13 |
| tnt | emeb_mac: I guess you just need driver for the serial ? | 07:15 |
| emeb_mac | tnt: that, plus the linker scripts and startup code. | 07:16 |
| emeb_mac | but I've already written most of the serial I/O routines needed so it should go together pretty well. | 07:16 |
| emeb_mac | there's a tutorial in the cc65 docs that pretty much lays out what's needed for an FPGA-based 6502 that's similar to what I did. | 07:17 |
| tnt | that's nice of them :) | 07:18 |
| emeb_mac | tnt: the makefile you linked has all kinds of cruft in it for existing 6502 systems (Commodore/Apple/Atari/etc) that's completely useless for this application. Would end up stripping 90% of that out. | 07:19 |
| emeb_mac | using the icestick limits the amount of ROM/RAM to just 8kB total and the system as-is uses about 80% of the fabric so this is nearing the limits. | 07:25 |
| emeb_mac | moving to a u4k or up5k will significantly increase the memory and periphs possible. SPRAM on the up5k opens things up significantly. | 07:26 |
| emeb_mac | but that'll wait until morning. | 07:26 |
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| corecode | woh these ecp devboards are expensive | 12:41 |
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| daveshah | The LFE5UM5G-85F-EVN isn't bad | 12:55 |
| daveshah | $99 for the biggest ECP5 and a year's diamond license | 12:56 |
| ylamarre | Define expensive? | 12:56 |
| corecode | oh you need a diamond license to use the ecp5? | 13:10 |
| corecode | that's a downer | 13:10 |
| daveshah | Yes, you need one to use any of the with SERDES variants | 13:11 |
| daveshah | The non SERDES ECP5s don't need a license | 13:11 |
| corecode | ok | 13:11 |
| corecode | crazy that this is a business model they can do | 13:11 |
| daveshah | I think it's so they can give them for free to their big customers, to make those customers feel special | 13:12 |
| corecode | lol | 13:12 |
| srk | the rest of us needs to wait for RE efforts and opensource toolchain :D | 13:16 |
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| somlo | daveshah, what's the relationship between https://github.com/YosysHQ/nextpnr/tree/placer_heap_ddrn (which I can't actually access anymore) and PR #219 ? | 18:01 |
| daveshah | placer_heap_ddrn was a rebase of placer_heap onto the ddr3 changes | 18:04 |
| daveshah | The latter are now merged into master | 18:04 |
| daveshah | And placer_heap/#219 are on top of that (and should be used( | 18:04 |
| keesj | is the physical constraint file format documented somewhere? | 18:15 |
| daveshah | No, it's a vaguely extended variant of the icecube format | 18:15 |
| keesj | ok | 18:16 |
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| somlo | daveshah: I've been using #219 for a few weeks now, as it's awesomely fast compared to *not* using it -- works great for my use case (rocket-chip on ecp5), will try using it on the ddr3 litedram SoC today... | 18:50 |
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| daveshah | Awesome, I'm hoping to have it upstreamed fairly soon | 18:51 |
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| keesj | can I add verilog files while in the yosys shell ? e.g. something like add but for verilog files | 19:27 |
| keesj | e.g. something like http://www.clifford.at/yosys/cmd_add.html | 19:29 |
| tpb | Title: Yosys Open SYnthesis Suite :: Command Reference :: add (at www.clifford.at) | 19:29 |
| keesj | found it (read_verilog) .. | 19:29 |
| keesj | http://www.clifford.at/yosys/cmd_read_verilog.html | 19:30 |
| tpb | Title: Yosys Open SYnthesis Suite :: Command Reference :: read_verilog (at www.clifford.at) | 19:30 |
| corecode | ERROR: Found error in internal cell $techmap\top.spi.$procdff$602 ($adff) at kernel/rtlil.cc:709: | 19:38 |
| corecode | what could that mean? | 19:38 |
| corecode | what did i do wrong? | 19:38 |
| daveshah | This was a recent regression, fix is merged I think. | 19:38 |
| corecode | ah thank you | 19:39 |
| daveshah | Does your Yosys have https://github.com/YosysHQ/yosys/pull/837? | 19:39 |
| tpb | Title: Fix multiple issues in wreduce FF handling, fixes #835 by cliffordwolf · Pull Request #837 · YosysHQ/yosys · GitHub (at github.com) | 19:39 |
| corecode | i'm building | 19:39 |
| corecode | and i'll check with latest master | 19:40 |
| daveshah | Latest master should be fine | 19:40 |
| corecode | yep that worked | 19:46 |
| corecode | hm, so now my simulation works, but doesn't seem to work on the fpga? | 19:53 |
| tnt | corecode: what are you trying to run ? | 19:53 |
| corecode | my forth cpu | 19:57 |
| tnt | on what board ? | 20:04 |
| corecode | my own, u4k | 20:10 |
| corecode | must be my mistake | 20:10 |
| corecode | pre-synthesis simulates right, post-synthesis does not | 20:10 |
| corecode | my write strobe gets lost | 20:11 |
| ylamarre | sim/synth mismatches are my favorites <3 | 20:12 |
| ZipCPU | ylamarre: I wrote about that once some time ago ... | 20:14 |
| ylamarre | Most of the time they are uninitialized signals getting compared to 0. | 20:14 |
| ZipCPU | I tried to categorize as many sim/synth mismatches as I could get ahold of--thanks to the reddit folks | 20:15 |
| ZipCPU | Uninitialized stuffs ... formal usually finds that for me, so that much is fairly simple | 20:15 |
| ylamarre | ZipCPU: Hi, haven't had time to go through all your stuff, but from what i've looked there were some very good articles, | 20:16 |
| ZipCPU | Thanks! | 20:16 |
| tnt | post-synthesis simulation is something I almost never do. Actally I rarely have something working in simulation and not in real hw. | 20:16 |
| corecode | wel this one doesn't :/ | 20:17 |
| ZipCPU | There's an icebox_vlog program that makes post-synthesis simulation very possible, even with Verilator. Not sure it works with the u4k or not. | 20:17 |
| tnt | do you have an explicit reset line ? (rather than relying on reg x = 1'b1) ? | 20:18 |
| corecode | ZipCPU: it does | 20:18 |
| corecode | i have a reset counter | 20:18 |
| corecode | haha | 20:22 |
| corecode | oh man, what a dumb mistake | 20:23 |
| corecode | always @(posedge clk) if (reset) sig <= 0; else if (clk) sig <= somethingelse; | 20:23 |
| corecode | not attentive, added a if(clk) | 20:23 |
| corecode | unclear why this made it not synthesize "properly" | 20:24 |
| corecode | and now it works! | 20:25 |
| tnt | if rising_edge(clk) ... VHDL FTW ! | 20:25 |
| corecode | not sure how that would have helped | 20:25 |
| tnt | corecode: congrats :) | 20:25 |
| tnt | That's the 'gotcha' with verilog ... if you deviate from the best practice / templates ... you get crap synthesis results | 20:26 |
| ylamarre | Where as with VHDL you'd get none? | 20:27 |
| tnt | exactly. with vhdl it would throw an error :) | 20:27 |
| tnt | (or you just can't ... like there is no blocking / non-blocking stuff in vhdl so you can't get it wrong) | 20:28 |
| ylamarre | Well, there is variables vs signals, but, I guess those are not exactly the same... | 20:29 |
| corecode | but shouldn't synthesis and simulation always agree? | 20:29 |
| tnt | yeah, variables are local to the process. | 20:29 |
| ylamarre | corecode: LOL | 20:29 |
| corecode | well, if not, there must be a bug in the implementations | 20:30 |
| ylamarre | Well the uninitialized compare to 0 is a good example of both implementation being rigth, but still mismatching. | 20:30 |
| tnt | corecode: no ... verilog allows you to describe non-deterministic logic. | 20:30 |
| tnt | http://insights.sigasi.com/opinion/jan/vhdls-crown-jewel.html | 20:31 |
| tpb | Title: VHDL's crown jewel - Sigasi (at insights.sigasi.com) | 20:31 |
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| emeb | tnt: having some success w/ cc65 building ROM for the 6502 project. Kind of amazed it worked first time. :) | 22:47 |
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| emeb | just need to setup a recursive make for it. | 22:49 |
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| tnt | emeb: Oh nice. Looking fwd to the up5k variant :p | 22:51 |
| emeb | tnt: should be easy | 22:51 |
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