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| corecode | hi | 11:43 |
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| ZipCPU | Yo! | 12:41 |
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| promach_ | What do you guys think about https://gist.github.com/promach/5f2d9a9494704ed93cf65687c982198c#file-multiply-v-L118 ? | 15:38 |
| tpb | Title: A signed multiply verilog code using row adder tree multiplier and modified baugh-wooley algorithm · GitHub (at gist.github.com) | 15:38 |
| daveshah | Implementing a full adder like that is going to give very poor results for FPGA synthesis | 15:39 |
| promach_ | daveshah: because of the topmost partial product layers ? | 15:44 |
| promach_ | wait, you were referring to full adder | 15:44 |
| daveshah | Because FPGA synthesis tools are unlikely to infer carry logic from a full adder written as logic rather than + | 15:44 |
| promach_ | what do you mean by "rather than +" ? | 15:45 |
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| daveshah | FPGA synthesis tools might not infer FPGA carry logic from AND/OR/XOR operators. They expect to see +/-/* operators to infer carries | 15:46 |
| daveshah | I doubt performance will be good without using the fast carry chains | 15:47 |
| promach_ | daveshah: I see, this is the line cout <= (ain & bin) | (cin & (ain^bin)); | 15:47 |
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| daveshah | Yes, I don't know why you aren't just using the Verilog + operator | 15:48 |
| daveshah | Unless this is for ASIC? Then it probably doesn't matter | 15:48 |
| promach_ | daveshah: cout <= (ain * bin) + (cin * (ain - bin)); | 15:51 |
| daveshah | You'd have to do it on a word | 15:51 |
| promach_ | ain, bin, cin, cout are of one bit | 15:52 |
| daveshah | Yes, exactly, this is probably going to end up with a poor FPGA mapping | 15:52 |
| daveshah | Just use a + b where a and b are words | 15:53 |
| promach_ | words ? | 15:53 |
| daveshah | Multiple bits | 15:53 |
| daveshah | A single-bit full adder module is almost always going to have poor FPGA results | 15:53 |
| promach_ | ok | 15:54 |
| promach_ | let me try both ways | 15:54 |
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| promach_ | Strange, I have multiple conflicting drivers warning for https://gist.github.com/promach/5f2d9a9494704ed93cf65687c982198c#file-multiply-v-L110-L113 | 16:43 |
| tpb | Title: A signed multiply verilog code using row adder tree multiplier and modified baugh-wooley algorithm · GitHub (at gist.github.com) | 16:43 |
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