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| keesj | https://fosdem.org/2019/schedule/event/trellis_and_nextpnr/ (video online of daveshah's presentation) | 09:37 |
|---|---|---|
| tpb | Title: FOSDEM 2019 - Project Trellis and nextpnr (at fosdem.org) | 09:37 |
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| shapr | ZipCPU: students asked if there's a docker image that has all the tools installed | 18:21 |
| shapr | might be a good thing for your tutorial | 18:21 |
| ZipCPU | shapr: Thanks for the suggestion! | 18:48 |
| ZipCPU | SymbioticEDA routinely creates Vagrant+VirtualBox images with all of the tools installed on them, but these are used when teaching the formal verification course. Those images come with a 90 day (?) license for the full Symbiotic EDA suite as well. | 18:49 |
| ZipCPU | I've thought about making a docker image, but ... know so little about what would be required to do so that I haven't even tried starting | 18:49 |
| shapr | fair enough | 18:56 |
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| sxpert | ZipCPU: care to help a beginner ? | 19:11 |
| ZipCPU | Sure, I could use a distraction, what's up? | 19:12 |
| sxpert | I am embarking in this https://github.com/sxpert/hp-saturn/blob/master/saturn_core.v | 19:12 |
| tpb | Title: hp-saturn/saturn_core.v at master · sxpert/hp-saturn · GitHub (at github.com) | 19:12 |
| ZipCPU | Go on | 19:13 |
| sxpert | when I launch the compile script, I don't seem to be getting much back out, what am I missing ? | 19:13 |
| ZipCPU | "compile script"? | 19:13 |
| sxpert | https://github.com/sxpert/hp-saturn/blob/master/compile | 19:13 |
| tpb | Title: hp-saturn/compile at master · sxpert/hp-saturn · GitHub (at github.com) | 19:13 |
| sxpert | this compile script | 19:13 |
| ZipCPU | Ok | 19:14 |
| ZipCPU | Can I ask you to make two changes and then come back and ask again? | 19:14 |
| sxpert | sure | 19:14 |
| ZipCPU | Change 1. Add: `default_nettype none // to the top of your source code | 19:14 |
| ZipCPU | Change 2: Run: verilator -Wall -cc saturn_core.v # on your source code | 19:15 |
| ZipCPU | That will find a lot of bugs in your code. When verilator -Wall comes back with no more warnings, then let's see what else might be going on. | 19:15 |
| sxpert | ok | 19:15 |
| daveshah | sxpert: to get a working ecp5 bitstream, you need to specify both --basecfg and --textcfg to nextpnr | 19:20 |
| daveshah | Then use ecppack on the output from textcfg | 19:20 |
| daveshah | See https://github.com/SymbiFlow/prjtrellis/blob/master/examples/picorv32_versa5g/Makefile#L17 | 19:20 |
| tpb | Title: prjtrellis/Makefile at master · SymbiFlow/prjtrellis · GitHub (at github.com) | 19:20 |
| sxpert | ZipCPU: there are indeed warnings, and even errors | 19:21 |
| sxpert | daveshah: ah, will look at that | 19:21 |
| ZipCPU | daveshah: I wasn't expecting that. Can you explain what's going on? Why does nextpnr need the extra information, but only for the ECP5? | 19:21 |
| sxpert | (once I have fixed those warnings) | 19:21 |
| ZipCPU | sxpert: Verilator's warnings are fairly easy to fix--especially compared to other tools (Cough Vivado cough cough Quartus) | 19:21 |
| daveshah | ZipCPU: because there are a few fixed bits needed for ecp5 bitstreams and I haven't got round to hardcoding them | 19:22 |
| daveshah | basecfg passes those | 19:22 |
| ZipCPU | So the basecfg argument is project independent? | 19:22 |
| daveshah | textcfg is the equivalent of --asc for the ice40 | 19:22 |
| daveshah | ZipCPU: yes, barring some very odd use cases | 19:22 |
| sxpert | daveshah: in the example $@ is replaced by attosoc_out.config ? | 19:22 |
| daveshah | sxpert: yes | 19:22 |
| sxpert | ok | 19:23 |
| ZipCPU | If textcfg is the equivalent of --asc, why not use --asc instead? | 19:23 |
| daveshah | ZipCPU: because its a different format with a different name | 19:23 |
| daveshah | sxpert: also make sure the textcfg you pass corresponds to the right ecp5 variant | 19:23 |
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| sxpert | daveshah: ah, looking for one for ULX3S with 85F | 19:35 |
| sxpert | then | 19:35 |
| sxpert | (which I just received in the mail) | 19:36 |
| daveshah | sxpert: https://github.com/SymbiFlow/prjtrellis/blob/master/misc/basecfgs/empty_lfe5u-85f.config | 19:36 |
| tpb | Title: prjtrellis/empty_lfe5u-85f.config at master · SymbiFlow/prjtrellis · GitHub (at github.com) | 19:36 |
| sxpert | thanks | 19:38 |
| sxpert | ZipCPU: I suppose warnings of the "blah is not used" (because it's not implemented yet) are not a problem | 19:39 |
| ZipCPU | sxpert: Let me show you how to get rid of them ... | 19:40 |
| ZipCPU | At the bottom of your design, but before the endmodule, insert the following lines: | 19:40 |
| ZipCPU | / Verilator lint_off UNUSED | 19:40 |
| ZipCPU | wire [N-1:0] unused; | 19:40 |
| ZipCPU | assign unused = { all of your unused nets}; | 19:40 |
| ZipCPU | / Verilator lint_on UNUSED | 19:40 |
| ZipCPU | You'll need to adjust N to the number of unused wires you have | 19:41 |
| ZipCPU | The neat thing about this is that, now when you use some of the bigger tools, they'll warn you about having an unused wire named: unused | 19:41 |
| ZipCPU | You can then quickly ignore that warning and go onto any others | 19:41 |
| sxpert | ZipCPU: I have something wierd line 142, it says RSTK is not used, but it is at various locations | 19:44 |
| ZipCPU | I just searched your design for RSTK | 19:45 |
| ZipCPU | It appears to be unused | 19:45 |
| ZipCPU | You reset it to zero, but then do nothing more with it | 19:45 |
| ZipCPU | There's some code referencing it, but it appears to be commented out | 19:45 |
| sxpert | I do assign things to it on line 783 | 19:46 |
| sxpert | (the contents of PC) | 19:47 |
| * ZipCPU looks | 19:47 | |
| ZipCPU | Can you update the github file, so I can see the updates you've made? | 19:47 |
| sxpert | push done | 19:48 |
| sxpert | (sorry) | 19:48 |
| * ZipCPU clones hp_saturn | 19:48 | |
| ZipCPU | Line 873 should have two /'s, not just one--same for line 876 | 19:49 |
| sxpert | ah, irc ate the first / ;-) | 19:50 |
| ZipCPU | You'll also need to adjust the N and the {} lines ... since you hadn't done that, I commented the two out | 19:50 |
| ZipCPU | Wow, that is one giant state machine | 19:51 |
| ZipCPU | I'm not sure line 306 is right, the case for READ_ROM_STA etc... | 19:51 |
| ZipCPU | Several tools have required I use a "begin end" on an empty case | 19:51 |
| sxpert | ah | 19:51 |
| ZipCPU | Line 438 too | 19:52 |
| sxpert | I can add that no pb | 19:52 |
| sxpert | (there are a bunch of those) | 19:52 |
| ZipCPU | Does anything reference RSTK? Or is it set only? | 19:53 |
| sxpert | it will be used when I get to implement the RTN* instructions | 19:54 |
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| ZipCPU | Sure, but then it's an unused register | 19:54 |
| ZipCPU | It's not that it isn't set, it's just unused | 19:54 |
| daveshah | Also, note the entire design will be optimised away for similar reasons | 19:55 |
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| sxpert | ZipCPU: ah, ok, that's what it means | 19:55 |
| daveshah | Because it has no outputs (other than one that is at a constant value) | 19:55 |
| sxpert | so I should connect say the leds, and show parts of a different register at each clock or something ? | 19:56 |
| daveshah | Yes, that would be a good solution | 19:56 |
| sklv | hi, i need an application which does RW on at least 2 sd cards at the same time, drives an oleds102 spi display, and transfers data over an rs232 port - i am trying to estimate whether this is withing my capability to implement with a verilog mcu - are there any examples of a boards where a yosys soft cpu runs code from external flash? | 19:56 |
| ZipCPU | sxpert: Have you seen my logic minimization article? http://zipcpu.com/blog/2017/06/12/minimizing-luts.html You might find it valuable | 19:56 |
| tpb | Title: Minimizing FPGA Resource Utilization (at zipcpu.com) | 19:56 |
| sklv | s/at the same time/not at the same time/ | 19:56 |
| sxpert | ZipCPU: not yet | 19:57 |
| ZipCPU | sklv: Yes | 19:57 |
| sklv | ZipCPU: can you link me please? | 19:57 |
| sxpert | ZipCPU: I am trying to get something that works first ^^ | 19:57 |
| ZipCPU | If by "external flash" you mean a flash chip external to the FPGA, then most definitely yes. | 19:57 |
| sklv | that's what i mean yea, but i want the flash to contain CPU code as opposed to FPGA configuration code | 19:57 |
| ZipCPU | sklv: How about this one, https://github.com/ZipCPU/icozip | 19:58 |
| tpb | Title: GitHub - ZipCPU/icozip: A ZipCPU demonstration port for the icoboard (at github.com) | 19:58 |
| ZipCPU | Or this one, https://github.com/ZipCPU/s6soc | 19:58 |
| tpb | Title: GitHub - ZipCPU/s6soc: CMod-S6 SoC (at github.com) | 19:58 |
| sxpert | sklv: it is my understanding you can have both | 19:58 |
| ZipCPU | Or even this one: https://github.com/ZipCPU/openarty | 19:58 |
| tpb | Title: GitHub - ZipCPU/openarty: An Open Source configuration of the Arty platform (at github.com) | 19:58 |
| sxpert | sklv: depending on the size of said config flash | 19:58 |
| ZipCPU | sxpert: For all the flash work I've done, I have yet to come near to even using a half of the flash | 19:59 |
| ZipCPU | Most flash devices have been plentiful for me | 19:59 |
| ZipCPU | sklv: Most of my designs using flash have used it for both the FPGA configuration as well as for CPU code | 19:59 |
| sklv | that's fine | 19:59 |
| sxpert | ZipCPU: sounds like a perfect fit for my application's rom code | 19:59 |
| ZipCPU | It can be, but do beware: It will take you many cycles to read from the flash | 20:00 |
| sxpert | ZipCPU: plan is to read it all to ram on boot | 20:00 |
| daveshah | How fast do you need to run at? | 20:00 |
| ZipCPU | Here's a good discussion of how the flash impacts a CPU: http://zipcpu.com/zipcpu/2018/03/21/dblfetch.html | 20:00 |
| tpb | Title: Pipelining a Prefetch (at zipcpu.com) | 20:00 |
| sxpert | ZipCPU: sdram that is | 20:00 |
| ZipCPU | sxpert: My OpenArty design reads from flash into SDRAM on boot | 20:01 |
| ZipCPU | Although I discuss it more on this page: http://zipcpu.com/zipcpu/2018/02/12/zbasic-intro.html | 20:01 |
| tpb | Title: Want to use ZBasic? Let's have some fun--no actual FPGA required! (at zipcpu.com) | 20:01 |
| sklv | ZipCPU: so what, artix7 can be handled with an open toolchain now? | 20:02 |
| sklv | i thought it was just lattice | 20:02 |
| sklv | how new is this just out of interest? | 20:02 |
| ZipCPU | sklv: The differences are irrelevant to the toolchain | 20:03 |
| sklv | oh it says in the repo | 20:03 |
| ZipCPU | sklv: I'm working on a blog entry regarding that repo right now | 20:03 |
| ZipCPU | The active work has been taking place within the autoarty branch | 20:03 |
| sklv | ok, icoboard looks good for my needs - what about anything with a hand solderable fpga so tqfp qfp qfn ? | 20:04 |
| * ZipCPU shudders at the word "solder" and runs in the other direction | 20:04 | |
| ZipCPU | :D | 20:04 |
| ZipCPU | sklv: You might need to ask someone else for soldering advice | 20:05 |
| daveshah | sklv: have a look at the ice40hx4k in the qfp package or the up5k in the qfn package if you don't want bga | 20:05 |
| daveshah | The former is the same silicon as is on the icoboard | 20:06 |
| sxpert | sklv: ask Louis Rossmann for soldering advice ;) | 20:07 |
| sklv | i don't need soldering advice, i want my fpga in a particular package, although that's been answered anyway :) | 20:08 |
| * ZipCPU takes a peek to see if it is safe to return to the channel | 20:08 | |
| * sxpert will continue implementing stuff | 20:10 | |
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