Monday, 2019-01-07

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sigwinch_	Good morning, #yosys!	08:45
daveshah	Morning sigwinch_!	08:45
sigwinch_	I was asking myself how to properly have a counter have the correct width, based on the number of cycles I want to count, and especially to get rid of a warning when I compare against "number of cycles minus one". Here's what I came up with, and I wanted to ask if that's the proper way or hopelessly ugly:	08:47
sigwinch_	https://pastebin.com/gHU0x1AU	08:47
tpb	Title: [VeriLog] verilog integer width - Pastebin.com (at pastebin.com)	08:47
daveshah	So personally I'd never worry about such a warning	08:49
daveshah	I think an alternative way might be to do (NCYCLES-1)[CYCLE_CTR_BITS-1:0]	08:50
sigwinch_	Ah, good idea, never thought of that (bit-indexing a integer literal).	08:51
swetland	I believe you need $clog2(N+1) if N could be an exact power of two	09:03
swetland	daveshah: I like the warning in general as it catches assignments of mismatch net-sizes to each other, but it does get entertaining when params/constants are involved	09:04
swetland	as I am reminded elsewhere, don't need the +1 on the clog2 if N-1 is the max value in use	09:14
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sigwinch_	daveshah: verilator doesn't like (123)[NBITS-1:0] ...	10:29
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sigwinch_	...and yosys doesn't like typedefs ;-).	10:31
swetland	try this in verilator:	10:32
swetland	localparam NCYCLES_1 = NCYCLES - 1;	10:32
swetland	NCYCLES_1[CYCLE_CTR_BITS-1:0]	10:33
swetland	it seems to be willing to slice a param but not an arbitrary expression	10:33
sigwinch_	:-) Very good. Seems to make both yosys, iverilog and verilator happy! Thanks!	10:36
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swetland	this has been the adventure of verilog/systemverilog for me -- finding the union of features/syntax/dialect that all the tools I want/need to use can understand	10:37
sigwinch_	https://pastebin.com/uStGp9mp	10:37
tpb	Title: [VeriLog] verilog counter with dynamic width, 0..(N-1), no warn - Pastebin.com (at pastebin.com)	10:37
swetland	so there's a neat trick for this that someone pointed out to me recently -- if you load the counter to max and then detect the underflow (making the counter one bit wider than you need to be), you don't need an n-bit-wide comparator to detect the trigger/reload -- you just trigger on underflow	10:45
tnt	sigwinch_: in general if you don't need the value, make counter 1 bit wider, init to xxx-2, doing a decrement and look for the msb going high. Avoids the need for a comparator.	10:45
tnt	Arf ... was too slow to type :	10:46
sigwinch_	That's a very useful remark, thanks tnt!	10:46
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sigwinch_	(and of course swetland ;-) ...)	10:52
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swetland	tnt's explanation was much more succinct -- worth the wait ^^	10:55
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sigwinch_	https://en.wikiquote.org/wiki/Blaise_Pascal - I would have written a shorter letter, but I did not have the time.	11:02
tpb	Title: Blaise Pascal - Wikiquote (at en.wikiquote.org)	11:02
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shapr	ZipCPU: hey! newbie verilog question ... is #mystorm a better place for me to ask?	19:01
ZipCPU	No, this is fine ... what's up?	19:01
shapr	restarted my FPGA class for the year	19:02
FL4SHK	FPGA class?	19:02
shapr	I want to get this FPGA-Synthesizer working on my beaglewire	19:02
FL4SHK	In school?	19:02
shapr	FL4SHK: yeah, I teach a Monday FPGA class here at my job	19:03
shapr	er, no	19:03
FL4SHK	oooh teach	19:03
shapr	FL4SHK: I don't actually know anything about FPGAs!	19:03
ZipCPU	FL4SHK: Corporate lunch time, sweet, huh?	19:03
shapr	that makes it more challenging :-P	19:03
FL4SHK	when I was doing my MS degree I did a bunch of HDL dev	19:03
ZipCPU	Ok, keep going ... synthesizer	19:03
shapr	FL4SHK: I did convince several of my coworkers to buy their own BeagleBone + BeagleWire	19:03
ZipCPU	I have the BBB ... just not the beagle wire	19:04
shapr	ZipCPU: I will happily send you one and some cash	19:04
shapr	you just have to remind me of your contracting fees again	19:04
shapr	aanyway	19:04
shapr	I forked an existing FPGA-Synthesizer	19:04
shapr	but the whole codebase relies on ... I think a 2MHz system-wide PLL	19:05
shapr	and the BeagleWire has a 1MHz? maybe it's 200MHz and 100MHz	19:05
shapr	in any case, all the clock division is done explicitly from the PLL on a Xilinx board	19:05
ZipCPU	Let's see ... you should be able to run the BeagleWire at about 50MHz, maybe more	19:05
shapr	ZipCPU: so my question is, do I need to just divide the existing counts by the difference between the Xilinx and BW clock speeds?	19:06
FL4SHK	Is the BeagleWire an FPGA board?	19:06
shapr	FL4SHK: yes!	19:06
FL4SHK	I see	19:06
FL4SHK	I'd never heard of it	19:06
shapr	FL4SHK: https://www.crowdsupply.com/qwerty-embedded-design/beaglewire/	19:06
tpb	Title: BeagleWire \| Crowd Supply (at www.crowdsupply.com)	19:06
shapr	FL4SHK: I chose it because you can install yosys directly on the board	19:06
shapr	and my earlier Haskell classes ran into problems installing on a wide variety of operating systems	19:06
ZipCPU	This is good ... keep going	19:07
shapr	ZipCPU: so I think this says the board this was built for is 500MHz: https://github.com/shapr/FPGA-Synthesizer/blob/master/synthesizer.v#L4	19:07
tpb	Title: FPGA-Synthesizer/synthesizer.v at master · shapr/FPGA-Synthesizer · GitHub (at github.com)	19:07
shapr	and I think this says the BeagleWire is 100MHz: https://elinux.org/BeagleBoard/BeagleWire#External_clock_source	19:08
tpb	Title: BeagleBoard/BeagleWire - eLinux.org (at elinux.org)	19:08
ZipCPU	You'll never get the iCE40 up to 500MHz!	19:08
ZipCPU	Sounds like you have a 100MHz clock input, go on	19:08
shapr	I figured I could hack this synthesizer source to work with out of the box beaglewire	19:09
shapr	then I could contribute it as an example	19:09
ZipCPU	Sounds good, go on	19:09
shapr	so my question comes down to "do I just divide all the explicit clock division by five?"	19:09
ZipCPU	Better to use a PLL ... you sure you don't want 50MHz? It's a nice frequency to work at ... ?	19:09
shapr	for example: https://github.com/shapr/FPGA-Synthesizer/blob/master/pmod_out.v#L39	19:09
tpb	Title: FPGA-Synthesizer/pmod_out.v at master · shapr/FPGA-Synthesizer · GitHub (at github.com)	19:09
shapr	why is 50MHz a good frequency?	19:10
shapr	hi FL4SHK ! How'd you end up in this nifty community?	19:10
ZipCPU	It's fast, and it's got plenty of room for logic	19:10
FL4SHK	shapr: ZipCPU's influence	19:10
* ZipCPU grins broadly		19:10
shapr	good reason!	19:10
shapr	FL4SHK: do you do FPGA stuff for money?	19:10
FL4SHK	I just got my first out-of-college job that I think will be involving that	19:10
shapr	oh cool! So you just finished your Master's? or you went on to get a doctorate?	19:11
FL4SHK	just finished my MS	19:11
shapr	nice!	19:11
* ZipCPU showed FL4SHK how to use formal verification methods on his college project. He told ZipCPU it'd never have worked without the formal methods.		19:11
shapr	I'd like to go back and get a master's but it did take me twenty four years from start to finish for my bachelor's	19:11
FL4SHK	oh	19:11
shapr	mind you, I really enjoy taking college classes	19:12
FL4SHK	some of mine I actually did really enjoy taking haha	19:12
shapr	I love learning far more than I care about grades	19:12
shapr	my GPA was never impressive, but when I learn something it sticks in my head forever	19:12
shapr	that's all I care about	19:13
* shapr swears at pagerduty		19:13
ZipCPU	shapr: If you want to configure a PLL, you'll need both icepll as well as the iCE40 documentation for their PLLs	19:13
shapr	for learning by others, why not just use stock BeagleWire 100MHz and modify the synthesizer to handle that?	19:14
shapr	also, verilog still makes me angry that I can't parameterize clocks	19:14
ZipCPU	You could	19:14
ZipCPU	It's not a bad idea	19:14
ZipCPU	Only problem with 100MHz is ... what happens if you can't get your logic running that fast?	19:14
ZipCPU	Jan Gray suggests, for high speed clocking, pick a clock rate and stick with it--so you might be good	19:15
ZipCPU	My problem is that I started with the ZipCPU at 100MHz on an Artix-7 device ... and so all my logic references are with respect to that experience.	19:15
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ZipCPU	shapr: What kind of speakers do you expect to be using? As in, what interface will they be expecting? I2S? PWM?	19:18
shapr	I have the i2s pmod from digilent that the original author used	19:18
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ZipCPU	What clock speed did he use for it? 1MHz?? That would seem rather odd.	19:19
shapr	i2s is a digital protocol	19:19
tmeissner	Does anyone tried to build SymbiYosys from source?	19:19
shapr	ZipCPU: pagerduty is being needy, I'll return sometime :-/	19:20
tmeissner	I cannot build Avy, I get compilation error	19:20
ZipCPU	tmeissner: I do it all the time	19:20
ZipCPU	shapr: ;)	19:20
tmeissner	I assume that the error results from implicit conversions which are now illegal with the latest C++ standard	19:21
ZipCPU	What machine are you building on? Ubuntu?	19:21
tmeissner	debian	19:21
tmeissner	error: narrowing conversion of '2500023266u' from 'unsigned int' to 'int' inside { } [-Wnarrowing]	19:22
ZipCPU	Let me check if I can build it (Ubuntu 16.04) ... it's been a while since I have	19:22
tmeissner	I get a lot of these during compile	19:22
ZipCPU	Those are probably not an issue	19:22
tmeissner	Not all, some are warnings, but these are errors and result in compilation abort	19:22
ZipCPU	What compiler are you using?	19:26
ddrown	is that gcc 8.x?	19:27
ZipCPU	As in ... what version of which compiler?	19:27
* ZipCPU is still using GCC 5.4		19:27
tmeissner	I don't know exactly, I used the apt-get line from the symbiyosys doc	19:27
tmeissner	I look after the version, please wait	19:27
ZipCPU	Try typing "gcc -v"	19:27
ZipCPU	It should show up on the last line of that output	19:27
tmeissner	gcc version 6.3.0 20170516	19:28
* ZipCPU just upgraded his avy, is about to start building ...		19:29
* shapr grumbles		19:29
shapr	ok so	19:29
shapr	ahem	19:29
shapr	ZipCPU: so I could just divide the clock division counts by five and it'll most likely all work?	19:29
ZipCPU	Generally, you should use a PLL if at all possible for any clock adjustments	19:30
shapr	what does that mean?	19:30
ZipCPU	Most FPGA devices have a series of special PLL hardware blocks within them	19:30
shapr	is the external clock of the BeagleWire not a PLL?	19:30
ZipCPU	No, that's a clock	19:31
ZipCPU	Imagine that to be an incoming square wave toggling at 100MHz	19:31
shapr	FL4SHK: if you ever want advice on writing Python or Haskell code, I can help :-)	19:31
shapr	sure, ok	19:31
ZipCPU	Your goal is to get some other rate ... 20MHz you said	19:31
FL4SHK	shapr: well tbh I've been programming for much longer than I've been writing HDL codehaha	19:31
shapr	yeah, different speeds for different things, yeah	19:31
FL4SHK	Haskell is kind of foreign to me though	19:31
shapr	FL4SHK: I can help!	19:31
FL4SHK	I've used Python enough times to be dangerous with it	19:31
shapr	if you want, not gonna be pushy	19:31
ZipCPU	While it is possible to do something like: always @(posedge i_100mhz_clk) o_20mhz_clk <= ... something appropriate ...	19:31
ZipCPU	You are likely to have all kinds of problems doing so	19:32
FL4SHK	ZipCPU: isn't the "correct" answer to use a counter instead	19:32
shapr	oh, I thought that was how clock dividers work	19:32
ZipCPU	Adjusting the clock speed with a PLL is recommended	19:32
FL4SHK	if (counter[...])	19:32
FL4SHK	at least in FPGA code	19:32
ZipCPU	FL4SHK: No.	19:32
shapr	this code does the counter thing: https://github.com/shapr/FPGA-Synthesizer/blob/master/pmod_out.v#L39	19:32
tpb	Title: FPGA-Synthesizer/pmod_out.v at master · shapr/FPGA-Synthesizer · GitHub (at github.com)	19:32
FL4SHK	eh?	19:32
FL4SHK	I'm not suggesting posedge counter[...]	19:33
FL4SHK	that much I know you're not supposed to do	19:33
ZipCPU	shapr: That should work nicely for creating outgoing clocks	19:33
ZipCPU	I was discussing internal clocks, such as you might use in the @(posedge CLOCK) section of your code	19:33
ZipCPU	The other stuff ... have at it	19:33
ZipCPU	;)	19:33
shapr	there's a difference?	19:33
ZipCPU	Yes	19:34
shapr	I thought the external clock was the same as a PLL	19:34
shapr	in that they're both clock signal sources	19:34
FL4SHK	you definitely don't want to do @(posedge counter)	19:34
FL4SHK	in... synthesizeable code	19:34
ZipCPU	If you use an always @(posedge something) ... use either an externally supplied clock or the output of a PLL (both will work)	19:34
FL4SHK	^	19:34
FL4SHK	if you want a "clock divider" without using a PLL I'm pretty sure you can do if (counter[...])	19:34
* ZipCPU considers sitting back and watching his apprentice teach the lesson ;)		19:35
shapr	FL4SHK: I've been using Python since 1996, but professionally only since 2000	19:35
shapr	dunno if I'm an expert, but I know more than most	19:35
shapr	FL4SHK: ok so... what's the difference between a PLL and an external clock?	19:35
shapr	is the difference that I can change a PLL?	19:35
shapr	is there any functional difference?	19:36
FL4SHK	PLLs need an external clock	19:36
shapr	oh they do?	19:36
FL4SHK	in terms of your FPGA code it probably doesn't matter which one you use?	19:36
FL4SHK	yeah	19:36
FL4SHK	PLLs are like magic to me	19:36
FL4SHK	but I have used them	19:36
shapr	so, a PLL on an FPGA needs an external clock to feed it, but then you can change the default clock speed of your entire .. something?	19:36
ZipCPU	FL4SHK: You didn't read my article on PLL's? ;)	19:36
ZipCPU	shapr: Yes.	19:37
FL4SHK	It'd be neat if I could just make a PLL out of logic but	19:37
ZipCPU	FL4SHK: You can ....	19:37
FL4SHK	Isn't that a bad idea	19:37
FL4SHK	I thought it was a bad idea lol	19:37
shapr	is it?	19:37
FL4SHK	Maybe I'm wrong	19:37
ZipCPU	In general, it is ... but some of the Xilinx hardware has some really curious and useful capabilities ... but we are getting off topic	19:37
ZipCPU	shapr: The basic idea is ... external clock -> (FPGA Boundary) -> PLL -> Clock at whatever rate you'd like (within reason)	19:38
shapr	ok, so a PLL can modify an incoming external clock	19:38
ZipCPU	Yes	19:38
shapr	but you don't get many PLLs?	19:39
ZipCPU	It can cause it to change phase and frequency. Some PLL's can also output multiple clocks with known relationships to each other	19:39
shapr	otherwise I could use them to do clock division for me?	19:39
ZipCPU	No, you don't get many at all.	19:39
ZipCPU	You don't want to use a PLL to create your I2S clocks	19:39
shapr	how is a PLL different from a counter that does clock division?	19:39
shapr	why not?	19:39
shapr	ZipCPU: I swear I need to send you more money	19:39
ZipCPU	Why? Because going through the PLL introduces some amount of ns delay	19:39
* ZipCPU does not object		19:39
* shapr fires up patreon		19:40
ZipCPU	If you are going to send data out of an FPGA, you really want to make certain all of that data transitions on the same clock interval--so it all has the same timing relationships within it	19:40
ZipCPU	A PLL will give you the right frequency, but will also change phase--usually undesirably--so that you nolonger maintain a known phase relationship with the incoming clock	19:41
somlo	ZipCPU, shapr: isn't the problem with wiring up your own custom PLLs that now your clock signal would be output over "data" wires rather than dedicated "clock" wires the FPGA might be distributing inside itself? (apologies for jumping in randomly like that into someone else's conversation thread :)	19:41
ZipCPU	Hello, somlo!	19:41
ZipCPU	Welcome to the discussion	19:41
shapr	ZipCPU: upgraded to "needy student" :-)	19:41
ZipCPU	Yes, that is one of the possible problems	19:41
ZipCPU	Another one has to deal with making sure the tools can properly do timing analysis on your design	19:42
shapr	since I'm already asking that kind of question	19:42
ZipCPU	It can be dfficult to do that with logic	19:42
ZipCPU	I discussed this in an article some time ago ... I just don't remember which one! :D	19:42
shapr	you have so much content!	19:42
ZipCPU	(It wasn't the main topic of the article)	19:42
shapr	I'm glad you have a patreon, I don't feel as bad about asking piles of stupid questions.	19:43
* ZipCPU changes the sentence structure: "You are so content" ... and likes that better		19:43
ZipCPU	lol	19:43
ZipCPU	shapr: Go on, am I helping out with your questions still?	19:44
shapr	yes!	19:44
ZipCPU	So ... I have an I2S controller I built some time ago but never used	19:45
shapr	ok, so PLL could have different phase, hm	19:45
ZipCPU	I got far enough along that I was at the point where I needed to configure the audio chip and ... that's where I got stuck	19:45
ZipCPU	Apparently, a lot of audio devices want some really weird frequency: 48.192 MHz or something like that	19:45
ZipCPU	Creating that frequency is ... not trivial	19:45
shapr	I will happily mail you a digilent i2s pmod to match the one I own	19:46
shapr	and a beaglewire	19:46
ZipCPU	Would love it!	19:46
shapr	heck, I'll mail you a whole kit of goodies	19:46
shapr	because then I can ask noobie questions about those goodies!	19:46
ZipCPU	So far, the only audio out I've done successfully has been with either PWM, or unintentional FM	19:47
ZipCPU	(well, intentional unintentional FM)	19:47
shapr	heh	19:47
ZipCPU	It turns out those GPIO wires can be made to "broadcast" at your favorite frequency ... :D	19:47
shapr	oh, did you see the hackaday article yesterday?	19:48
ZipCPU	One project of mine involved playing Queen on my favorite local Christian radio station	19:48
ZipCPU	Which one?	19:48
shapr	https://hackaday.com/2018/12/06/your-usb-serial-adapter-just-became-a-sdr/	19:48
tpb	Title: Your USB Serial Adapter Just Became a SDR \| Hackaday (at hackaday.com)	19:48
ZipCPU	No, I hadn't seen that one ... I'll look forward to reading it	19:49
tmeissner	ZipCPU I've found a forum wheresome users of ArchLinux ran into the same compile error	19:50
ZipCPU	tmeissner: You might consider trying to build one of the other Avy branches ... you might find it builds easier, but I can't comment on whether or not it would work better	19:50
tmeissner	ZipCPU they fixed it by adding a option to cmake that gcc don't take these errors only as warning	19:51
ZipCPU	Sounds like a good temporary patch	19:51
tmeissner	ZipCPU the master branch of avy is pretty old (2015), so maybe you're right, that one of the other branches don't have this problem	19:52
ZipCPU	Looks like most of the work is being done in the new_quip branch	19:52
ZipCPU	There's also a quip branch which appears to have been stable for half a year or so	19:52
tmeissner	Let's try the new_quip first, I'm a adventurer today :D	19:53
shapr	ZipCPU: so your suggestion was to change the clock signal on the BeagleWire to match the 500MHz of the original board?	19:55
shapr	no wait...	19:55
* shapr reads back		19:55
ZipCPU	500MHz? What runs at 500MHz? The example you shared had 500 kHz in it ..	19:55
shapr	er, I thought the incoming clock was 500MHz for the xilinx board this synthesizer was created to run on?	19:56
ZipCPU	Not likely, that's way too fast	19:56
shapr	https://github.com/shapr/FPGA-Synthesizer/blob/master/pmod_out.v#L7 ?	19:56
tpb	Title: FPGA-Synthesizer/pmod_out.v at master · shapr/FPGA-Synthesizer · GitHub (at github.com)	19:56
ZipCPU	I'm pretty sure that's a typo	19:57
daveshah	Given they seem to divide by 25 to get 2MHz it must be a 50MHz clock	19:58
shapr	oh yeh!	19:58
ZipCPU	The code is broken as well ... line 39 shows a classic off-by-one error	19:58
daveshah	Which is much more plausible	19:58
shapr	I just realized that!	19:58
shapr	I'm glad you two can read better than I can	19:59
ZipCPU	daveshah: But they aren't creating 2MHz anywhere ... are they? I'm only seeing kHz number	19:59
ZipCPU	numbers	19:59
daveshah	Well "2000kHz"	19:59
daveshah	Actually 1923kHz as you say	19:59
ZipCPU	Ahh ... okay, that starts to make more sense. I think the incoming clock though is 100MHz though	19:59
ZipCPU	Since they appear to be dividing the incoming clock by 52 ((25+1)*2)	20:00
ZipCPU	(I think that's a bug by the way--you can tell that whoever wrote this didn't formally verify it :D )	20:00
daveshah	It depends if that comment refers to the frequency that block runs at or the frequency of the clock it creates	20:00
daveshah	I also see they have a non constant initial value for sig_tmp	20:01
* shapr reads https://en.wikipedia.org/wiki/I%C2%B2S		20:01
shapr	daveshah: what does that mean?	20:02
daveshah	*sig_temp	20:02
daveshah	See the initial block	20:02
daveshah	The initial value is set to the sig input	20:02
daveshah	This is not feasible in FPGA hardware, and wouldn't make much sense if it was	20:02
shapr	What's sig?	20:03
shapr	daveshah: you have context I am missing, what does that imply?	20:03
daveshah	https://github.com/shapr/FPGA-Synthesizer/blob/master/pmod_out.v#L30	20:03
tpb	Title: FPGA-Synthesizer/pmod_out.v at master · shapr/FPGA-Synthesizer · GitHub (at github.com)	20:03
tmeissner	ZipCPU new new_quip branch compiles nearly to the end, but then there is another error, it can't find some file of the boost library	20:04
daveshah	In hardware this would imply sampling sig at the moment the FPGA boots to initialise sig_temp	20:04
shapr	and that's bad?	20:04
daveshah	But FPGAs can't do that	20:04
tmeissner	I will have a look, if it's somewhere else	20:04
daveshah	The synthesis tool will either ignore it with a warning or error out	20:04
shapr	sounds like I should try to throw this codebase into yosys and then squander ZipCPU's time with noobie questions	20:04
* shapr sighs		20:05
* ZipCPU clones the repo		20:05
shapr	on the good side, it seems like my question has turned into much useful information for me!	20:05
* ZipCPU starts adding formal properties ...		20:05
shapr	haha	20:05
shapr	daveshah: I thought sig was passed into the module?	20:06
* ZipCPU renames MCLK o_i2s_mclk, LRCLK as o_i2s_lrclk, SCLK as o_i2s_sclk, etc.		20:07
* ZipCPU replaces output name with output reg name		20:08
* ZipCPU adds `default_nettype none to the top		20:08
daveshah	shapr: yes it's an input to the module (and therefore not a constant, or at least not guaranteed to be one)	20:08
* ZipCPU replaces input clk with input wire i_clk		20:09
daveshah	Yosys will probably error out, most tools will ignore it with a warning	20:09
daveshah	As synthesis tools are free to ignore initial blocks if they want too, either behaviour is arguably correct	20:09
* ZipCPU replaces sig_temp <= sig; with sig_temp = 0;		20:09
* ZipCPU removes "<=" from the initial block, replacing it with "="		20:10
* ZipCPU notes that this code never passed a verilator -Wall test		20:10
* ZipCPU finds blocking assignments where there should be non-blocking assignments ... (See MCLK = ~MCLK)		20:11
* ZipCPU finds references to the (blocking assignment results) at the end of the file. These explain why he thought there was a divide by 26		20:13
* ZipCPU notices a lack of a reset, and then tugs at his beard pondering		20:14
somlo	daveshah: prjtrellis examples (https://github.com/SymbiFlow/prjtrellis/tree/master/examples) mention a TinyFPGA Ex board with an 85k ECP5; however, the TinyFPGA EX at https://tinyfpga.com says it's using a LFE5U-25F (i.e., 25k). Did they have a limited-edition 85k one, or is that a typo?	20:15
tpb	Title: prjtrellis/examples at master · SymbiFlow/prjtrellis · GitHub (at github.com)	20:15
somlo	daveshah: nvm, I meanwhile found https://www.crowdsupply.com/tinyfpga/tinyfpga-ex :)	20:19
tpb	Title: TinyFPGA EX \| Crowd Supply (at www.crowdsupply.com)	20:19
shapr	ZipCPU: I know some of those things	20:35
shapr	does that mean you should not do <= in the initial block?	20:36
ZipCPU	Verilator can't handle "<=" within an initial block	20:37
ZipCPU	Yosys can't handle "=" within a memory initialization in an initial block	20:37
ZipCPU	Sigh	20:37
shapr	how would I recognize a memory initialization?	20:38
shapr	I should read all the ZipCPU tutorials first	20:38
* ZipCPU rummages		20:38
ZipCPU	Memory initialization is currently discussed in my (still draft) lesson 8: Block RAM	20:39
ZipCPU	Let me post a slide from that lesson though ..	20:40
ZipCPU	https://imgur.com/75NQl7G	20:40
tpb	Title: Imgur: The magic of the Internet (at imgur.com)	20:40
ZipCPU	Here's some of the rules I use to make certain the memories I create/define are inferred properly: https://imgur.com/a/cISRlrS	20:43
tpb	Title: Imgur: The magic of the Internet (at imgur.com)	20:43
ZipCPU	I think rule #2 is perhaps the most common frustration among beginning designers using memory	20:44
shapr	oh	20:46
shapr	ram init seems sensible enough	20:46
shapr	ZipCPU: if you have multiple always blocks, do they act as one?	20:47
ZipCPU	Officially: No Unofficially, it might depend by what you mean	20:47
ZipCPU	I typically write my designs with as many always blocks as I have variables, or just shortly less than that--mostly for cost savings	20:47
shapr	mostly wondering if multiple always blocks in the same module are equivalent to one always block with the same code	20:48
ZipCPU	Roughly, yes, but it doesn't work in reverse	20:48
shapr	because ordering?	20:48
ZipCPU	Ordering, yes, and also references to things within the block	20:49
ZipCPU	The simulator is free to pick whatever order it wants to execute the always blocks using	20:49
ZipCPU	This is where blocking (=) vs non-blocking (<=) gets ugly	20:49
shapr	yeesh	20:50
shapr	not sure I actually like verilog	20:50
ZipCPU	If you have a blocking (=) assignment in one always block, and a reference to the value in another, which will get executed first?	20:50
shapr	but it's what I have	20:50
ZipCPU	You'll also have problems with Verilator ... it doesn't handle blocking assignments (=) very well	20:50
ZipCPU	To avoid hardware/simulation mismatch, always use the non-blocking operator (<=) within any clocked always block, and the blocking operator (=) within any combinatorial always block	20:51
ZipCPU	(That much was in the tutorials ... see lesson two)	20:51
tmeissner	I think there are some goop papers from sunburst regarding thi problems with (non)blocking assignments	20:52
ZipCPU	Could be ... but I don't remember seeing any such papers	20:52
ZipCPU	I might need to look again--that would be valuable	20:52
adamgreig	what's the deal with always @* begin bla = 1'h0; bla = some_other_sig; end	20:52
tmeissner	But the hint of ZipCPU is best for beginners I think	20:52
adamgreig	odd syntax for initialise to 0 and thereafter combinatorially equal to some_other_sig?	20:53
ZipCPU	adamgreig: Not at all. the first assignment will be ignored in favor of the second.	20:53
tmeissner	I can remember to some Verilog 4 VHDL users course at Doulos. And this problem was handled very at the beginning	20:53
adamgreig	where bla is "reg bla"	20:53
adamgreig	ZipCPU: so the first assignment is meaningless?	20:53
somlo	"always @*" is combinational, though (always_comb in System Verilog)	20:53
ZipCPU	adamgreig: Yes	20:54
adamgreig	yea, so why would you write two blocking assignments in a combinatorial block to the same register?	20:54
somlo	as opposed to always @(some_edge some_signal), which is where you'll want to limit yourself to nonblocking	20:54
somlo	adamgreig: so you can have Verilog sort things out for you: bla = 0; if (something) then blah = 4'hF; else ... etc	20:57
adamgreig	i mean just literally "reg foo; always @* begin foo = 1'h0; foo = other_sig; end"	20:57
somlo	you get a default value, and if some conditions are true you might end up assigning something else -- but you'll always have assigned something to it	20:57
somlo	I think that's redundant (legal, but the 1'h0 thing gets optimized out)	20:58
ZipCPU	Here are some good rules: https://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf	20:58
ZipCPU	See page 5 for example	20:59
adamgreig	hmm I think the intent here is probably assigning initial values	21:01
adamgreig	this is yosys-generated verilog from rtlil	21:02
ZipCPU	No, I don't think so, since that wouldn't assign an initial value	21:02
ZipCPU	I think the intent is to make sure some value, any value, is assigned--to avoid latches	21:02
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