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| phire | What's the best way to generate a netlist with proper names on the flipflops? | 05:31 |
|---|---|---|
| phire | Modify the proc_dff (and subsequent passes) to generate and perserve names? | 05:32 |
| phire | write some kind of post-processing script or pass that generates a name based on the output wires? | 05:32 |
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| daveshah | phire: imo, a fix that generated names for cells based on output wire name would be very useful | 09:18 |
| daveshah | s/fix/pass/ | 09:19 |
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| puddingpimp | it seems like it would be useful if there was a traceable link from every AST node to the pass and input AST node(s) that produced it | 11:55 |
| puddingpimp | but I guess that presumes that the prior AST state is stashed away somewhere | 11:55 |
| puddingpimp | I'm just an observer and not that familiar with yosys internals | 11:56 |
| phire | The previous state is deleted on each pass | 11:57 |
| puddingpimp | I do know that, I'm part of the way through te yosys manual atm | 11:58 |
| phire | the src attributes really should be propergated to every single generated node | 12:02 |
| puddingpimp | so there is the HDL AST and then the yosys AST (from what I understand) does the HDL AST from the lexer stick around in memory? | 12:04 |
| phire | Well, you can save out the IL at any point and load it into a new instance of yosys later | 12:06 |
| puddingpimp | how early/late is the AST flattened, eg. if I have 4 instances of a module A, which has two instances of module B, is module A and B optimised once each and then flattened, | 12:07 |
| puddingpimp | or is the whole AST flattened before any later processing | 12:07 |
| phire | I think the typical workflow is to run the hierarchy pass early on before optimising, which I understand flatterns the design. | 12:13 |
| daveshah | read_verilog does by default elaborate & simplify the AST with the default parameter set for a module (turned of with -nodefer); but keeps the AST around in case the module is encountered with a different set of parameters | 12:14 |
| daveshah | hierarchy will elaborate all modules as instantiated with their parameter set | 12:14 |
| daveshah | flattening is optional at this point, and pretty much unrelated to elaboration of the AST | 12:15 |
| phire | One problem with the manual, is that it doesn't really give you much idea which passes you should be running in which order | 12:17 |
| daveshah | There is a bit on this in the appnotes at the end | 12:18 |
| daveshah | tldr; always run hierarchy and proc before anything else | 12:18 |
| phire | Yeah | 12:19 |
| phire | Right now I'm trying to generate nice looking schematics of my design | 12:19 |
| daveshah | Have you seen https://github.com/nturley/netlistsvg? | 12:20 |
| tpb | Title: GitHub - nturley/netlistsvg: draws an SVG schematic from a JSON netlist (at github.com) | 12:20 |
| phire | yeah, I'm considering improving it | 12:20 |
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| phire | I think I actually want a "looks good in schematic form" technology library. | 12:24 |
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