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| ANINDITA | hii while checking for timing constraint in yosys i get two warnings Directive set_load should be followed by two arguments. | 07:14 |
|---|---|---|
| ANINDITA | also for driving cell | 07:15 |
| ANINDITA | what is the solution to avoid the warnings | 07:15 |
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| ZipCPU | ANINDITA: Is this an ASIC design? | 12:57 |
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