Sunday, 2018-06-24

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promach_in smtbmc, what actually drives the always clocked block ?01:08
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promach_awygle cr1901_modern : have you tried induction check on UART under multiclock ?15:49
awyglepromach_: no15:50
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promach_awygle: this multiclock induction is driving me nuts16:17
promach_I really have no idea what went wrong16:17
promach_I mean the bug location16:17
promach_wait, I think I just found it out16:19
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lutsaboundIs zipcpu the only one who has formally verified his uart using dissimilar clocks?17:15
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awyglei'm not completely sure i understand what you're asking about. which "dissimilar clocks"? you mean verifying the asynchronous input?18:12
lutsaboundI mean using one  clock for the transmitter and another for the receiver when verifying the receiver18:14
awyglemy receiver was verified with up to a 5% difference in nominal vs. actual data rate, if that's what you mean. i didn't verify it with totally independent clocks because i verified it post-synchronizer, so everything was in the same clock domain.18:24
awyglethis seemed like a reasonable assumption as long as (UART data rate) << (system clock rate), which it almost always is. i verified at i think 16x oversampling but it would be easy to do more.18:25
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lutsaboundTwo questions: is your  code posted somewhere (and where), and two: did you use bmc only, or induction as well18:36
awygleit's posted here: https://github.com/awygle/spirit/tree/uart_lite_wip/uart_lite but that looks like it's missing some things. i haven't worked on this in months (since March apparently). i'll try and update it in the future, but the approach at least should be clear here18:39
tpbTitle: spirit/uart_lite at uart_lite_wip · awygle/spirit · GitHub (at github.com)18:39
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lutsaboundThanks!18:49
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awygleno problem. i'm still not totally satisfied with that design - it feels too permissive - but it was a good exercise and i haven't had time to go back and try to clean it up18:53
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