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| * ZipCPU just built a JSON parser for Yosys outputs .... it wasn't all that hard to do | 03:01 | |
| sorear | after the first half of that i was expecting a json parser in verilog | 03:02 |
|---|---|---|
| ZipCPU | Lol! Thank you sorear, that brought a smile to my face. | 03:02 |
| sorear | (you are aware of azonenberg's verilog protobuf parser?) | 03:03 |
| ZipCPU | Not at all. Care to share? | 03:03 |
| ZipCPU | I was more commenting for azzizi's sake. Indeed, the JSON format was so easy to parse, I'm tempted to build a BLIF parser next. Shouldn't be too hard. | 03:05 |
| sorear | i just know it exists ( https://github.com/azonenberg/protohdl ) and have heard some discussion about it, i don't think i could explain it in detail | 03:06 |
| tpb | Title: GitHub - azonenberg/protohdl: Streaming FPGA/ASIC code generator for Google Protocol Buffers. (at github.com) | 03:06 |
| ZipCPU | Sadly, the readme doesn't tell me much. | 03:07 |
| sorear | yeah, I noticed | 03:16 |
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| daveshah | sorear: I think a JSON parser in Verilog would be easier than the MATLAB one azzizi is suggesting | 07:03 |
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| qu1j0t3 | haha | 11:48 |
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| aiju | is there no mailing list? | 16:37 |
| awygle | i don't believe there is a yosys mailing list | 16:38 |
| awygle | would you prefer that over IRC or reddit? | 16:38 |
| daveshah | there's also stackoverflow | 16:39 |
| daveshah | but no mailing list. github issues and pull requests are used for that sort of stuff. | 16:39 |
| aiju | yeah i guess i'll make an issue on github | 16:39 |
| daveshah | aiju: what is your problem? | 16:41 |
| aiju | it's a bug in the liberty parser | 16:42 |
| aiju | https://github.com/YosysHQ/yosys/issues/569 | 16:44 |
| tpb | Title: Liberty parser fails to parse expressions like !A !B · Issue #569 · YosysHQ/yosys · GitHub (at github.com) | 16:44 |
| daveshah | aiju: don't know anything about the liberty parser, but thanks for submitting the issue | 16:45 |
| daveshah | clifford will look at it | 16:45 |
| aiju | it also barfs on some flipflop because it gets confused by IQ but i don't know enogh about the liberty format to tell what's going on | 16:46 |
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| cr1901_modern | >(2:59:48 AM) daveshah: sorear: I think a JSON parser in Verilog would be easier than the MATLAB one azzizi is suggesting | 18:09 |
| cr1901_modern | Not done/committed yet, but libhammer will eventually have a parser backend for FPGAs | 18:09 |
| daveshah | oh that's awesome | 18:10 |
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