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| mithro | Is there a way to prevent yosys from "optimizing" a design / lut away? | 00:17 |
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| awygle | (* KEEP *) i think? | 00:21 |
| mithro | awygle: yeah - actually that seems to have worked... | 00:27 |
| awygle | HTH lol | 00:29 |
| mithro | awygle: Do you know what the best way to create a LUT5 in the ice40 is? | 00:31 |
| cr1901_modern | Prob from 3 LUT4s? | 00:43 |
| puddingpimp | can probably compress into 2 LUT4s in many cases | 00:54 |
| awygle | mithro: I'm not aware of a better way than "write one in Verilog" | 00:55 |
| mithro | awygle: I was more interested in how you might pack the needed structures for a LUT5 together into a cell for an efficient design | 00:57 |
| awygle | mithro: ah. No particularly good ideas. | 01:04 |
| mithro | awygle: Like I feel like the LUT cascade or something might be useful | 01:04 |
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| mattvenn | cool interview with Clifford Wolf here: https://theamphour.com/374-an-interview-with-clifford-wolf/ | 14:55 |
| mattvenn | cool interview with Clifford Wolf here | 14:55 |
| mattvenn | woops | 14:55 |
| mattvenn | lots of interesting stuff, and last 30 minutes is all about formal verification | 14:55 |
| awygle | tinyfpga was also on amp hour recently, which was cool | 15:25 |
| awygle | and Michael Ossman shouted out azonenberg during his segment | 15:26 |
| awygle | we gotta get some open fpga folks on embedded.fm, the podcast I actually listen to :-P | 15:27 |
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| mattvenn | I only just heard about that one | 16:25 |
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| azzizi_ | Hello | 17:09 |
| azzizi_ | What should be the sequence of commands to convert verilog to bench files ..? | 17:09 |
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| azzizi_ | Can I upload any picture here ? | 17:12 |
| ZipCPU | No, but you can upload a picture to imgur.com and post the link here. | 17:13 |
| ZipCPU | A picture might help to understand what it is you want to do. | 17:14 |
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| azzizi_ | Please check : https://imgur.com/a/XPxt8wf | 17:21 |
| tpb | Title: Imgur: The magic of the Internet (at imgur.com) | 17:21 |
| azzizi_ | My ultimate goal is to prepare .bench file from given TrustHUB benchmarks so that I will be able to prepare a graph (using .bench). From this graph, I will be able to extract features of a circuit such as Logic Gate Fan-in, Multiplexer input/output, loops in a circuit or any other information of circuit that can be included in a dataset. | 17:22 |
| azzizi_ | I have also checked this :https://www.reddit.com/r/yosys/comments/85rm6u/a_problem_in_converting_into_bench_format/ | 17:23 |
| tpb | Title: A problem in converting into bench format : yosys (at www.reddit.com) | 17:24 |
| azzizi_ | My question is what should be the proper sequence of commands to convert | 17:24 |
| azzizi_ | benchmarks are verilog files btw | 17:26 |
| ZipCPU | azzizi_: Yosys doesn't have a write_bench command | 17:26 |
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| ZipCPU | azzizi_: To know the commands yosys supports, feel free to run "yosys" in its interactive mode and then issue the command "help" | 17:34 |
| ZipCPU | All of the various write formats will show up at the end of the list. | 17:34 |
| azzizi_ | So I can't use write_bench in Yosys but in ABC right ? | 17:37 |
| ZipCPU | That sounds about right | 17:38 |
| azzizi_ | So may I ask if you think I should include the 'techmap' and the 'dfflibmap -liberty mycells.lib' commands? | 17:39 |
| ZipCPU | I'm not much of an expert with the techmap commands, so I'd have to defer to someone else for that answer. | 17:40 |
| azzizi_ | Thank you ..should I wait here ? I am curious because these two commands are only different to what Clifford suggested in the reddit link I had posted earlier | 17:41 |
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| ZipCPU | Let's see if daveshah is around at all ....? | 17:42 |
| awygle | azzizi_: are you currently doing the techmapping and then the bench writeout is failing? | 17:43 |
| awygle | or are you currently *not* including the techmap commands | 17:43 |
| azzizi_ | <Zipcpu> Also in the imgur it is written that the write_bench command is for ABC I think maybe | 17:44 |
| azzizi_ | <awygle> Please check this : https://imgur.com/a/XPxt8wf, I am exactly using this sequence | 17:45 |
| awygle | ah | 17:45 |
| azzizi_ | Nothing is failing though...but I wonder if I am doing it correctly | 17:45 |
| azzizi_ | because the .bench and .blif format that I am getting, do not have a regular pattern from which I can proceed further. In .bench files I am getting LUTs instead of gates. I gates in .bench and .blif files are incomprehensible | 17:46 |
| awygle | and you're expecting NAND's instead of LUTs. | 17:46 |
| awygle | you need to pass your liberty file to your techmap command, i think | 17:47 |
| awygle | you're only mapping FFs to your liberty file, not anything else, so everything else is yosys internal cells, which apparently are LUTs | 17:47 |
| azzizi_ | May I bother you by asking what the proper sequence of commands should be | 17:48 |
| awygle | i think it should be as simple as replacing `techmap` with `techmap -map mycells.lib`. but i've never done anything like this, so this is educated guesswork. | 17:49 |
| azzizi_ | Thanks very much for the response | 17:50 |
| awygle | hmm actually, if that doesn't work, try adding `abc -liberty mycells.lib` after the dfflibmap pass | 17:50 |
| awygle | and that is the extent of my ability (and desire) to guess at this. good luck! | 17:51 |
| azzizi_ | Okay I will let you know the update | 17:51 |
| azzizi_ | thanks again | 17:51 |
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