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| mithro | Anyone know why arachne is not using the global network for this clock signal? | 02:07 |
|---|---|---|
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| mithro | https://www.irccloud.com/pastebin/UJdcqnoG/ | 02:11 |
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| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 02:11 |
| mithro | My understanding is that arachne should have chosen glb_netwk_4 as io_tile 0 9 io_0 can be routed directly onto glb_netwk_4? | 02:13 |
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| awygle | i can't comment on whether that tile correctly maps to glb_netwk_4 in the part you're using, but i do know arachne's global promotion rules are fairly primitive | 02:24 |
| awygle | so it's possible it's just deciding not to promote | 02:24 |
| mithro | awygle: Any way to force it? | 02:48 |
| awygle | mithro: manually instantiate the primitive? | 02:48 |
| awygle | There are examples of how to do that in icefuzz/tests/sb_gb.v and sb_gb_io.v | 02:49 |
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| awygle | I know how to force arachne *not* to promote but I don't think you can do the opposite except from verilog. | 02:50 |
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| promach | awygle: For temporal induction, why https://i.imgur.com/yIQ2dTm.png does not follow assertion in line 277 ? | 03:26 |
| promach | just for info, line 277 had passed BMC | 03:26 |
| promach | https://github.com/promach/UART/blob/development/rtl/test_UART.v#L277 | 03:26 |
| tpb | Title: UART/test_UART.v at development · promach/UART · GitHub (at github.com) | 03:26 |
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| awygle | lol hi promach | 03:33 |
| awygle | You almost certainly want {cnt{1'b0}} for one thing | 03:34 |
| promach | I have already tried that | 03:34 |
| awygle | Then you're probably not asserting enough intermediate steps to pass induction | 03:35 |
| awygle | I don't have time right now to fully work through your logic though | 03:35 |
| awygle | Try running with some of the other proof engines and see if you get a proof there, maybe | 03:36 |
| awygle | Like abc pdr | 03:37 |
| promach | awygle: ok | 03:39 |
| mithro | .gate SB_GB USER_SIGNAL_TO_GLOBAL_BUFFER=clk$2 GLOBAL_BUFFER_OUTPUT=clk$2$2 | 03:49 |
| mithro | .attr loc "0,9/2" | 03:49 |
| mithro | awygle: That seems to me like it decided to use User->Global routing rather than using the IO->Global routing... | 03:52 |
| awygle | mithro: yeah, looks like | 03:52 |
| awygle | did you instantiate it manually? | 03:53 |
| mithro | awygle: No - looking at the code - it looks like it always promotes in this way.... | 03:53 |
| awygle | huh, weird | 03:53 |
| awygle | I sort of remember there being something weird about the IO global routing but you need daveshah to tell you more | 03:54 |
| awygle | Also possible that cseed just didn't bother with the other kind | 03:54 |
| mithro | awygle: https://github.com/cseed/arachne-pnr/blob/master/src/global.cc#L482-L522 | 03:55 |
| tpb | Title: arachne-pnr/global.cc at master · cseed/arachne-pnr · GitHub (at github.com) | 03:55 |
| awygle | mmmyup | 04:00 |
| mithro | awygle: Were as I want this -> https://github.com/cseed/arachne-pnr/blob/52e69ed207342710080d85c7c639480e74a021d7/tests/simple/sb_gb_io.blif#L34-L35 | 04:02 |
| mithro | Right? | 04:02 |
| tpb | Title: arachne-pnr/sb_gb_io.blif at 52e69ed207342710080d85c7c639480e74a021d7 · cseed/arachne-pnr · GitHub (at github.com) | 04:02 |
| awygle | oh yeah daveshah actually mentioned that in openfpga awhile back | 04:02 |
| awygle | that looks reasonable yeah | 04:03 |
| awygle | https://irclog.whitequark.org/~h~openfpga/2018-05-09#22045733 this page of logs has the bulk of the discussion I had with daveshah about globals, and some discussion of arachne's behavior between daveshah and whitequark | 04:10 |
| tpb | Title: ##openfpga on 2018-05-09 — irc logs at whitequark.org (at irclog.whitequark.org) | 04:10 |
| mithro | I don't quite get this example -> https://github.com/cseed/arachne-pnr/blob/52e69ed207342710080d85c7c639480e74a021d7/tests/simple/sb_gb_io.v | 04:12 |
| tpb | Title: arachne-pnr/sb_gb_io.v at 52e69ed207342710080d85c7c639480e74a021d7 · cseed/arachne-pnr · GitHub (at github.com) | 04:12 |
| mithro | Shouldn't there be a "wire clk;" in there? | 04:13 |
| mithro | https://www.irccloud.com/pastebin/cvhB2Cr7/ | 04:16 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 04:16 |
| mithro | That seems to do what I want... | 04:16 |
| awygle | default_nettype strikes again | 04:16 |
| awygle | implicit wires are entirely legal | 04:17 |
| mithro | Anyone know how to solve "ERROR: Failed to import cell $techmap\gate.$procdff$7 (type $dff) to SAT database." ? | 04:23 |
| mithro | It seems like global nets are now being output by vpr correctly..... | 04:24 |
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| mithro | awygle: any idea? | 04:26 |
| mithro | daveshah: I'm assuming you haven't gotten up yet... | 04:26 |
| awygle | mithro: huh. No clue. Looks like a problem with your equivalence check and not necessarily the circuit tho. | 04:41 |
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| mithro | awygle: Makes it hard to check though :-P | 04:47 |
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| keesj | alright . I was done waiting for the tinyFPGA and ordered a icestick | 11:28 |
| keesj | this is the 4th ice board I ordered but will be the first one I have in my hands | 11:30 |
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| mattvenn | I have a question about dynamic circular left shift | 16:37 |
| mattvenn | I'm having a go at implementing an FFT in verilog | 16:37 |
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| mattvenn | I'm following along with this paper git remote add origin [email protected]:mattvenn/fpga-fft.git | 16:38 |
| mattvenn | woops | 16:38 |
| mattvenn | http://web.mit.edu/6.111/www/f2017/handouts/FFTtutorial121102.pdf | 16:38 |
| mattvenn | and for the ordering of the butterfly pairs, we can get the order by a left shift of the level and index of the butterfly | 16:39 |
| mattvenn | it's something that I would have thought would be easy to do in hardware | 16:39 |
| mattvenn | but what I've ended up with is concatenating the register twice so as I shift it I don't lose bits | 16:39 |
| mattvenn | git remote add origin [email protected]:mattvenn/fpga-fft.git | 16:40 |
| mattvenn | dang! This link: https://github.com/mattvenn/fpga-fft/blob/7c90dddd19a9fd072872658dbe8b31f06fe2a2da/hdl/agu.v#L44 | 16:40 |
| tpb | Title: fpga-fft/agu.v at 7c90dddd19a9fd072872658dbe8b31f06fe2a2da · mattvenn/fpga-fft · GitHub (at github.com) | 16:40 |
| mattvenn | which seems a waste of flops | 16:40 |
| mattvenn | any suggestions on how to improve this? | 16:40 |
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| mattvenn | I've just seen a paper on the sliding DFT | 17:37 |
| mattvenn | looks much simpler, why would I use a DFT over a sliding DFT? | 17:38 |
| mattvenn | as in the Cooley-Tukey implementation | 17:38 |
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| ZipCPU | As I recalled, I didn't have much struggle doing the bit reverse in my own pipelined FFT implementation | 18:06 |
| ZipCPU | Are you doing this in a pipelined or block fashion? | 18:06 |
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| knielsen | a dynamic bit shift is often called a "barrel shifter" - it does take some extra logic over a fixed shifter | 18:30 |
| ZipCPU | Yeah, but ... a bit reverser doesn't require a shifter at all | 18:31 |
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| knielsen | that's probably true :-) | 18:32 |
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| mithro | Does anyone here know how to read the output of a failed equivalence check from yosys? | 20:26 |
| mithro | The output I have is https://paste.ubuntu.com/p/dgzVfk4Wpc/ | 20:28 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 20:28 |
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| mithro | ZipCPU: any idea? | 20:37 |
| * ZipCPU is taking a peek | 20:37 | |
| mithro | daveshah: ^ | 20:38 |
| daveshah | Have a look at the cmp signals | 20:38 |
| * ZipCPU has yet to (successfully) try out the equivalence checking capability of yosys | 20:38 | |
| daveshah | If they are low, there is a mismatch | 20:38 |
| daveshah | There might be a way to get a vcd file, but I'm not sure | 20:40 |
| daveshah | The other option is just to simulate the two for 1000 cycles | 20:40 |
| daveshah | mithro: try adding -dump_vcd <file.vcd> to the sat command | 20:41 |
| daveshah | Then you'll get an easier to observe counterexample trace | 20:42 |
| mithro | 518 \cmp_LED2 0 0 0 | 20:43 |
| mithro | 518 \gate_LED2 0 0 0 | 20:44 |
| mithro | 518 \gold_LED2 1 1 1 | 20:44 |
| daveshah | That's clearly the first mismatched | 20:44 |
| daveshah | The vcd file will be clearer | 20:44 |
| mithro | daveshah: Well I think 514 is? | 20:44 |
| daveshah | Yeah it is actually | 20:46 |
| mithro | daveshah: Okay -- I have the vcd file | 20:50 |
| daveshah | What's it looking like in gtkwave? | 20:52 |
| mithro | daveshah: http://hopper.mithis.com/~tim/out.vcd | 20:52 |
| daveshah | Not at computer now | 20:52 |
| mithro | daveshah: It seems to go wrong when "trigger" goes high.... | 20:54 |
| daveshah | mithro: I think that's a SAT solver output indicating that it's gone wrong | 20:54 |
| daveshah | Can you post a screenshot where it goes wrong? | 20:54 |
| mithro | https://usercontent.irccloud-cdn.com/file/zZVnnsD1/image.png | 20:58 |
| daveshah | Looks like LED2 is broken | 21:00 |
| daveshah | mithro: can you post the HLC and the bitstream Verilog? | 21:00 |
| mithro | daveshah: https://paste.ubuntu.com/p/nZQPRSHXqr/ HLC | 21:01 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 21:01 |
| daveshah | Thanks | 21:02 |
| mithro | daveshah: https://paste.ubuntu.com/p/HNf2wvT8TS/ generated verilog | 21:04 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 21:04 |
| mithro | daveshah: Can icebox_vlog use the .sym stuff? | 21:04 |
| daveshah | mithro: yes | 21:04 |
| daveshah | Although it gets tacked on at the bottom | 21:05 |
| mithro | daveshah: IE Is there a way to get the verilog output to be nicer.... | 21:05 |
| daveshah | As a bunch of assigns | 21:05 |
| mithro | Looks like icebox_vlog has "-L lookup symbol names (using .sym statements in input)" | 21:07 |
| daveshah | Yes | 21:08 |
| daveshah | I can't immediately see what is wrong tbh | 21:08 |
| daveshah | Personally I'd simulate the icebox_vlog output to make sure it's not an equiv check issue first | 21:09 |
| mithro | daveshah: Any idea if the .sym can go through HLC | 21:09 |
| daveshah | No | 21:09 |
| daveshah | Not sure | 21:09 |
| mithro | Guess I'll just generate a separate .sym file and cat it onto the end of the asc file... | 21:13 |
| mithro | daveshah: I'd actually like to do some more LUT tests to make sure the LUT init is okay.... | 21:14 |
| daveshah | mithro: I'd say that's the most likely issue | 21:14 |
| daveshah | The routing looks OK at a glance | 21:15 |
| daveshah | Maybe VPR is swapping LUT pins or something weird? | 21:15 |
| daveshah | It's clearly almost right... | 21:15 |
| daveshah | 3 bits work fine | 21:15 |
| mithro | daveshah: I also wonder if something around resets? | 21:15 |
| mithro | daveshah: But I can't see anything around resets in the verilog? | 21:16 |
| daveshah | mithro: No, I don't think so | 21:16 |
| daveshah | That all looks fine | 21:16 |
| daveshah | But definitely run it through a simulator so you can see all the internal signals | 21:16 |
| mithro | daveshah: now I need to figure out how to do that :-P | 21:21 |
| daveshah | mithro: it would be a nice makefile target to have | 21:22 |
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| mithro | daveshah: Agreed | 21:24 |
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| daveshah | mithro: https://github.com/cliffordwolf/icestorm/blob/master/examples/icestick/Makefile#L22-L26 | 21:26 |
| tpb | Title: icestorm/Makefile at master · cliffordwolf/icestorm · GitHub (at github.com) | 21:26 |
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| mithro | daveshah: Guess I could try and pnr these demos.... | 21:44 |
| daveshah | mithro: yeah, give it a go | 21:44 |
| mithro | Now if only my icesticks would make it to me instead of going on a mail trip around multiple buildings.... | 21:45 |
| daveshah | These again take many clock cycles to do anything, so you'll have to either reduce the divider or run a long simulation | 21:45 |
| mithro | daveshah: I should be able to just run the test bench, right? | 21:51 |
| daveshah | mithro: yes | 21:59 |
| daveshah | But it might take a little while | 22:00 |
| daveshah | For such a simple design should be fine though | 22:00 |
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