*** tpb has joined #yosys | 00:00 | |
*** cemerick_ has quit IRC | 00:31 | |
*** Kitlith has quit IRC | 00:35 | |
*** Kitlith has joined #yosys | 00:43 | |
*** promach_ has joined #yosys | 01:13 | |
promach_ | For temporal induction, Could anyone advise why https://i.imgur.com/yIQ2dTm.png does not follow assertion in line 277 ? | 02:05 |
---|---|---|
promach_ | just for info, line 277 had passed BMC | 02:20 |
*** rqou has quit IRC | 03:39 | |
*** leviathan has joined #yosys | 03:39 | |
*** rqou has joined #yosys | 03:39 | |
promach_ | https://github.com/promach/UART/blob/development/rtl/test_UART.v#L277 | 03:41 |
tpb | Title: UART/test_UART.v at development · promach/UART · GitHub (at github.com) | 03:41 |
*** dxld has quit IRC | 03:53 | |
*** dxld has joined #yosys | 03:54 | |
*** promach_ has quit IRC | 03:55 | |
*** seldridge has joined #yosys | 04:23 | |
*** emeb_mac has quit IRC | 07:10 | |
*** _whitelogger has quit IRC | 07:22 | |
*** _whitelogger has joined #yosys | 07:24 | |
*** Guest23074 is now known as jayaura | 07:35 | |
*** seldridge has quit IRC | 07:36 | |
*** promach has quit IRC | 08:01 | |
*** dys has joined #yosys | 08:27 | |
*** promach has joined #yosys | 08:53 | |
*** proteus-guy has quit IRC | 09:22 | |
*** mjoldfield has joined #yosys | 09:22 | |
*** proteus-guy has joined #yosys | 09:23 | |
*** dys has quit IRC | 09:24 | |
*** _whitelogger has quit IRC | 10:22 | |
*** _whitelogger has joined #yosys | 10:24 | |
*** jwhitmore has joined #yosys | 10:39 | |
*** dys has joined #yosys | 10:50 | |
*** clifford has quit IRC | 11:17 | |
*** quigonjinn has joined #yosys | 12:35 | |
*** promach_ has joined #yosys | 12:47 | |
ZipCPU | promach_: You are going to find it difficult for someone to comment on your code based upon just a couple lines. | 13:03 |
ZipCPU | Your logic spreads across many files, the trace doesn't make much sense without a thorough understanding of how your logic works. | 13:03 |
ZipCPU | Worse, those couple of lines you are struggling with are long lines that are difficult to read and follow. | 13:04 |
*** quigonjinn has quit IRC | 13:04 | |
*** AlexDani` has joined #yosys | 13:23 | |
*** AlexDaniel has quit IRC | 13:24 | |
*** mjoldfield has quit IRC | 13:44 | |
*** mjoldfield has joined #yosys | 13:48 | |
promach_ | ZipCPU: you are right, but not with line 277 | 14:00 |
promach_ | shift_reg should follow assertion at line 277 in induction | 14:00 |
*** mjoldfield has quit IRC | 14:26 | |
*** mjoldfield has joined #yosys | 14:44 | |
*** emeb_mac has joined #yosys | 14:58 | |
*** m_t has joined #yosys | 15:12 | |
*** seldridge has joined #yosys | 16:04 | |
*** m_t has quit IRC | 16:13 | |
*** leviathan has quit IRC | 16:38 | |
*** promach_ has quit IRC | 16:39 | |
*** leviathan has joined #yosys | 16:42 | |
*** seldridge has quit IRC | 17:06 | |
*** seldridge has joined #yosys | 17:20 | |
ZipCPU | promach: The number of bits on the right hand side of that equation should match the number of bits on the left. | 17:52 |
*** AlexDani` is now known as AlexDaniel | 18:28 | |
*** m_t has joined #yosys | 18:31 | |
*** proteusguy has joined #yosys | 18:38 | |
*** seldridge has quit IRC | 18:47 | |
*** ralu has quit IRC | 18:52 | |
*** ralu has joined #yosys | 18:52 | |
*** ralu has quit IRC | 18:57 | |
*** ralu has joined #yosys | 18:57 | |
*** sklv has quit IRC | 19:02 | |
*** sklv has joined #yosys | 19:03 | |
*** leviathan has quit IRC | 19:15 | |
*** emeb has joined #yosys | 19:30 | |
*** seldridge has joined #yosys | 20:16 | |
*** m_t has quit IRC | 20:25 | |
*** kensan has joined #yosys | 20:58 | |
*** dys has quit IRC | 21:33 | |
*** seldridge has quit IRC | 21:58 | |
*** jwhitmore has quit IRC | 22:37 | |
*** danieljabailey has quit IRC | 23:04 | |
*** danieljabailey has joined #yosys | 23:04 |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!