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| ZipCPU | So ... does the SAT induction solver work from the (potential) assertion error timestep backwards, or from a generic timestep forwards? | 00:04 |
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| dmin7 | ZipCPU: i tried to simplify the read and write to the 2d array (triggers) .. in the simulation it runs fine, but it still gets synthesized as FFs and not BRAM .. any idea? | 12:00 |
| dmin7 | https://pastebin.com/jGPc69BJ | 12:00 |
| tpb | Title: [VeriLog] module icosoc_mod_triggerrec #( parameter integer CLOCK_FREQ_HZ = 0, // unused - Pastebin.com (at pastebin.com) | 12:00 |
| * ZipCPU takes a peek | 12:01 | |
| dmin7 | that was fast (: | 12:01 |
| ZipCPU | I think you'll still want to split the always block with if (triggers_*) up into two blocks. | 12:02 |
| * dmin7 go try | 12:02 | |
| ZipCPU | You mentioned a 2D array. I don't see any 2D arrays. I see a 1D array of 32-bit words. Is this what you meant by a 2D array? | 12:03 |
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| dmin7 | oh, yes .. just array* sorry | 12:05 |
| dmin7 | splitting it up doesn't change anything | 12:05 |
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| dmin7 | oh | 12:17 |
| dmin7 | you also told me to not use the for loop for initialization | 12:17 |
| dmin7 | without it it uses BRAM :o | 12:18 |
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| ZipCPU | ;) | 12:46 |
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| ZipCPU | So, after formally verifying the CPU, the extra logic I added to pass grew the CPU by about 5% LUTs. :/ | 14:47 |
| emeb | The perfect circuit is like the speed of light - you have to add exponentially more resources to get asymptotically close to the goal. | 14:52 |
| ZipCPU | The good news, I guess, is that I've just corrected a whole bunch of otherwise deadly hidden bugs within the CPU | 15:00 |
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