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| cr1901_modern | https://hastebin.com/gotukewidi.sql I found this mystery yosys script (not commited). Corresponds to this repo: https://github.com/cr1901/gp4-tests | 02:10 |
|---|---|---|
| cr1901_modern | Last modified: Aug 25, 2016 | 02:10 |
| tpb | Title: GitHub - cr1901/gp4-tests: A set of test Verilog sources for the GreenPAK 4 to exercise openfpga functionality. (at github.com) | 02:10 |
| cr1901_modern | Pretty sure I didn't start formal verification till May 2017? | 02:10 |
| cr1901_modern | A mystery indeed ._. | 02:10 |
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| dmin7 | hmm .. so it seems like icosoc and also picosoc can't actually address the spi flash after initialization (on the icezero). | 11:12 |
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| dmin7 | is there any icosoc / picosoc examples out there that have the spi flash directly attached to the ice40 and external pi/micro that i might have missed? | 11:14 |
| dmin7 | i found the micropython port | 11:14 |
| dmin7 | the black ice ii (icosoc) .. but that just removes all of the spi flash components | 11:15 |
| dmin7 | tinyfpga .. but it doesn't seem like he pushed any changes to the picosoc fork | 11:15 |
| dmin7 | and this, i guess: https://github.com/grahamedgecombe/picosoc-uip | 11:16 |
| tpb | Title: GitHub - grahamedgecombe/picosoc-uip: uIP 0.9 PicoSoC/PicoRV32 port (at github.com) | 11:16 |
| dmin7 | the micropython port would be interesting, but it gives me a "micropython.blif:10708: fatal error: unknown formal `CLKHFEN[0]'" after changing the chip and package name and .pcf assignments to the 4K | 11:19 |
| daveshah | dmin7: there is no internal oscillator in the 4k | 11:41 |
| daveshah | you will have to modify it use an external clock input | 11:41 |
| ZipCPU | daveshah: You've done a lot of work with the picosoc, right? Have you ever tried to set up the flash to start immediately on power up? | 11:48 |
| daveshah | ZipCPU: I've only ever used "plain" picosoc, which is always configured like that | 11:49 |
| daveshah | I've never used icosoc | 11:49 |
| daveshah | The micropython example for example just boots straight from flash | 11:49 |
| daveshah | dmin7: a plain picosoc example that does this is in the base picorv32 repo: https://github.com/cliffordwolf/picorv32/tree/master/picosoc | 11:50 |
| tpb | Title: picorv32/picosoc at master · cliffordwolf/picorv32 · GitHub (at github.com) | 11:50 |
| daveshah | you'll just need to change the pin assignments for the icezero | 11:51 |
| ZipCPU | Thanks! | 11:51 |
| dmin7 | daveshah: i tried that, doesn't run either .. i have to double check things tho | 11:52 |
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| daveshah | dmin7: you might need to change the UART divider, if your clock is different? | 11:53 |
| daveshah | looking at the icezero its clock is 100MHz | 11:53 |
| daveshah | so you'll need to reduce that, probably using a PLL | 11:54 |
| daveshah | 12MHz is I think what that example is designed for | 11:54 |
| dmin7 | a lit led would be fine for a start (: | 11:57 |
| dmin7 | the picorv32 should run fine with the 100mhz clock tho? | 11:57 |
| daveshah | dmin7: 100MHz is probably a bit fast for picorv32 on iCE40 | 11:58 |
| daveshah | you'll have to see what icetime says when running your design through it | 11:59 |
| dmin7 | it says: nope | 12:07 |
| dmin7 | :) | 12:07 |
| dmin7 | .. ok, i'll try to get picosoc running with lower clock then | 12:07 |
| dmin7 | thx | 12:07 |
| dmin7 | (maybe on the icoboard/icosoc the XO2 chip does do more than just passing thru the SPI signals 1:1?) | 12:10 |
| daveshah | dmin7: Yeah it might be you have to set an IO before the SPI signals get passed through | 12:11 |
| daveshah | I'm not sure | 12:11 |
| dmin7 | hmm .. terminate called after throwing an instance of 'std::out_of_range' | 12:35 |
| dmin7 | what(): map::at | 12:35 |
| dmin7 | make: *** [Makefile:24: hx8kdemo.asc] Aborted (core dumped) :S | 12:35 |
| dmin7 | (https://pastebin.com/0xRKfW5A https://pastebin.com/ib2x4JAL ) | 12:37 |
| tpb | Title: [Bash] [picosoc]$ make hx8kprog yosys -ql hx8kdemo.log -p 'synth_ice40 -top hx8kdemo - - Pastebin.com (at pastebin.com) | 12:37 |
| daveshah | dmin7: you can't use clk directly and through a PLL40_PAD at the same time | 12:39 |
| daveshah | it's a terrible error message I know | 12:40 |
| daveshah | you can remove the reset counter, and just connect resetn to locked | 12:40 |
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| mazzoo | playing on picosoc; why can't I insert the PLL as main clock? icetime says 30MHz is possible, but even with 12MHz (==input xtal) the runtime stalls | 15:24 |
| daveshah | mazzoo: What board are you using? | 15:26 |
| daveshah | Several popular boards have broken VccPLL wiring | 15:26 |
| mazzoo | axelsys breakout board | 15:27 |
| mazzoo | pll works fine for standalone a 135MHz VGA sig gen | 15:27 |
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| mazzoo | upscaling from the 12M xtal | 15:30 |
| daveshah | mazzoo: should be OK then | 15:31 |
| daveshah | Can you post your complete design somewhere? | 15:31 |
| daveshah | Do you have resetn driven by pll locked? | 15:32 |
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| mazzoo | daveshah: oh, i ignore pll lock, but there's a resetn counter | 15:33 |
| daveshah | Try connecting resetn to locked | 15:33 |
| mazzoo | thx | 15:34 |
| daveshah | The clock output may otherwise be unstable for a bit and cause problems by corrupting state | 15:35 |
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| mazzoo | works perfect. | 15:45 |
| mazzoo | <3 | 15:45 |
| mazzoo | thanks again! | 15:45 |
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| daveshah | mazzoo: awesome! | 15:50 |
| develonepi3 | Hello Pin C8 is my USER_CLK comes from a 100MHz osc. It is connected to IOT_197_GBIN1 on HX8K. | 16:01 |
| develonepi3 | When I try using it for as an input to PLL I get the fatal error: bad constraint on `i_clk': no PLL at pin C8. | 16:01 |
| develonepi3 | Can only certain pins be used as inputs to PLL? | 16:04 |
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| daveshah | develonepi3: use the SB_PLL40_CORE instead of SB_PLL40_PAD variant (and REFERENCECLK in instead of PACKAGEPIN) | 16:07 |
| develonepi3 | Thanks will check that out. | 16:10 |
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| thoughtpolice | I have a bit of an odd question, perhaps. I'm basically just trying to get some cell numbers on a large design when mapped to an ASIC gate library (.lib) -- but one issue is that when I do synthesis, all of my RAMs in the original design are mapped to DFFs, which clearly skews the metric; in reality these would be SRAMs or whatever. Does anyone know of a good way to ignore memory->DFF conversion for some part of the hierarchy? | 18:31 |
| daveshah | thoughtpolice: its just a case of not running the "memory" pass on those parts to leave the memory as a black box I think | 18:44 |
| daveshah | But I'm not sure of the details | 18:44 |
| thoughtpolice | Yeah, I just realized I stupidly had a 'memory' hanging out in my script. *facepalm* | 18:45 |
| thoughtpolice | But that does seem to be the right track and was my original thought; blackbox it somehow | 18:46 |
| ravenexp | is there any timeline for yosys 0.8 release? | 18:46 |
| daveshah | ravenexp: I think I heard some time over the summer. | 18:47 |
| ravenexp | it seems like it went from 1/2 years between releases to 1 1/2 years | 18:48 |
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| dmin7 | hmm, so i did some SPI debugging. seems picosoc starts to read the flash from offset 0 and then stops after about 130kB and then nothing happens ever thereafter .. | 20:17 |
| dmin7 | (like https://unsee.cc/d5006076/) | 20:18 |
| tpb | Title: Unsee Free online private photos sharing (at unsee.cc) | 20:18 |
| dmin7 | i also noticed that 'make spiflash_tb' fails with a lot of errors, but i guess that has nothing to do with it s) | 20:19 |
| daveshah | dmin7: I wouldn't worry about the testbench | 20:22 |
| daveshah | Can you post your top module now? | 20:22 |
| dmin7 | https://pastebin.com/iXtDJvG3 | 20:25 |
| tpb | Title: [VeriLog] /* * PicoSoC - A simple example SoC using PicoRV32 * * Copyright (C) 201 - Pastebin.com (at pastebin.com) | 20:25 |
| dmin7 | went down to 2mhz for testing | 20:25 |
| daveshah | dmin7: looks fine to me | 20:26 |
| dmin7 | i do get a 2mhz clock and it looks quite stable on my DSO Quad mini x) | 20:26 |
| daveshah | Can you post a LA trace including CS please? | 20:27 |
| dmin7 | LA trace? | 20:28 |
| * dmin7 rather new to the whole of this :) | 20:28 | |
| daveshah | Logic analyser trace - like before, but also with chip select | 20:30 |
| dmin7 | oh, good question .. i don't have it in there because last time it wouldn't let me flash anymore when i connected the CS to the logic analyzer too | 20:32 |
| dmin7 | which might be a hint that there is sth wrong with CS? x) | 20:32 |
| * dmin7 go try again | 20:33 | |
| dmin7 | yip, does not like to be connected to the LA | 20:36 |
| dmin7 | (the whole test setup is a bit of a mess atm because i had to connect everything with cables, but i guess if it works for the CLK etc it shouldn't be problem for CS either, already tried switching the gpio pin on the pi and using a different cable for CS) | 20:38 |
| daveshah | That seems a bit weid | 20:40 |
| daveshah | Is this an icoboard or an icezero again? | 20:41 |
| dmin7 | icezero | 20:41 |
| daveshah | So no MachXO involved then | 20:42 |
| dmin7 | yes | 20:42 |
| dmin7 | it works when i put 460ohm resistor before the LA :o | 20:43 |
| daveshah | Just thinking, reading 130kB from flash 0x0 sounds suspiciously like the fpga loading its bitstream | 20:43 |
| daveshah | Oh interesting | 20:43 |
| dmin7 | shouldn't those inputs be high impedance? | 20:43 |
| dmin7 | with working i mean i can make a trace, not that it runs (: | 20:44 |
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| daveshah | Yes, they should be | 20:45 |
| daveshah | It might be the LA's capacitance causing issues | 20:45 |
| daveshah | Or possibly even a bad pin assignment on CS, so it's floating? | 20:45 |
| dmin7 | https://unsee.cc/7d02d967/ | 20:48 |
| tpb | Title: Unsee Free online private photos sharing (at unsee.cc) | 20:48 |
| dmin7 | that is the whole "boot" .. so same size as before ~130k | 20:49 |
| daveshah | Yep, that's the fpga booting up | 20:50 |
| daveshah | Looks like the processor never starts | 20:50 |
| daveshah | Is resetn going high as expected? | 20:50 |
| daveshah | I'm afraid that's all I can think of for tonight. Happy to help again tomorrow though | 20:54 |
| dmin7 | i think it might be time for a break here also .. thx a lot! | 20:58 |
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