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| ZipCPU | Hi, tito_! Did you read through those tutorials? | 00:28 |
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| tito_ | hi | 00:34 |
| ZipCPU | Hi, tito_! Did you read through those tutorials? | 00:34 |
| tito_ | you are still tying zbasic on zipcpu ....... and also Verilator, but I'm still stationary ........... I have installed CYGWIN but I can not use it .......... .. | 00:38 |
| ZipCPU | Really? Why not? | 00:38 |
| ZipCPU | What's the problem? | 00:39 |
| tito_ | he i use windows and if i can i use powershall ........... ga what i know i have to start make :( | 00:41 |
| ZipCPU | Did you see my blog post regarding installing cygwin? It doesn't require or use powershell ... | 00:42 |
| tito_ | link to please | 00:43 |
| ZipCPU | http://zipcpu.com/blog/2017/07/28/cygwin-fpga.html | 00:44 |
| tpb | Title: Windows FPGA designers may not need a Linux machine ... yet (at zipcpu.com) | 00:44 |
| ZipCPU | I have to be careful that those instructions don't get out of date, so please let me know if you run into problems. | 00:45 |
| tito_ | I read, thanks | 00:45 |
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| bog_dan_ro | hello, does yosys support xilinx CPLDs (XC9572XL)? | 12:01 |
| daveshah | bog_dan_ro: As I understand it, Yosys can do basic synthesis and mapping using ABC for sum-of-product architectures, but does not support many more advanced CPLD features | 12:05 |
| daveshah | There is no bitstream generation support for that CPLD, but rqou is working on that (and PAR support and Yosys improvements) for the CoolRunner-II | 12:05 |
| bog_dan_ro | daveshah: thanks a lot, i"ll keep an eye on github ;-) | 12:09 |
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