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| mattvenn | ZipCPU: thanks for the article | 07:36 |
|---|---|---|
| mattvenn | so if I just ensure that the target register has enough width, I don't need to care about any intermediate steps that may be larger? | 07:37 |
| mattvenn | I'm sure I'm missing something | 07:37 |
| mattvenn | like if I have a = b * c - d * e | 07:38 |
| mattvenn | where does the b * c intermediate result happen before the subtract? | 07:39 |
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| ZipCPU | mattvenn: I do tend to care about the immediate steps. Perhaps I don't need to care as much, but I do. | 13:01 |
| ZipCPU | The biggest issue I've come across is signed vs unsigned, and width mismatches. | 13:01 |
| ZipCPU | If you use { x, b, c} to adjust the width of an object, the object becomes unsigned. | 13:01 |
| ZipCPU | If you don't adjust the width ... some synthesis tools complain. | 13:01 |
| ZipCPU | Theoretically a <= b*c - d*e; should "just work". | 13:03 |
| ZipCPU | Practically, I personally always break it down. | 13:03 |
| ZipCPU | For example, I'm not sure there's hardware out there that will support that operation in a single clock. You could go faster if you broke it into two: | 13:04 |
| ZipCPU | tmp_left <= b*c; tmp_right <= d*e; a <= tmp_left + tmp_right; | 13:04 |
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| mattvenn | ok, which also makes it obvious how big tmp_left and tmp_right should be | 13:16 |
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| cr1901_modern | signed vs unsigned in Verilog is a mess, esp wrt multiplication. It's terse, but I recommend reading the verilog spec for this :'9 | 15:12 |
| cr1901_modern | ;'(* | 15:12 |
| cr1901_modern | :'(* damnit | 15:12 |
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