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| ZipCPU | Yaayy!!! Got my first yosys patch accepted. Yosys now suppoprts string literals containing \a, \f, \v, and (my favorite) \r. | 11:45 |
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| qu1j0t3 | yeah, \r is kind of important. | 12:17 |
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| daveshah | ZipCPU: congratulations :) | 12:44 |
| keesj | \o/ | 13:07 |
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| kristianpaul | :) | 13:31 |
| wumpus | nice | 13:47 |
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| shapr | I got the ice40 board for my novena, but I have no idea how to load a bitstream onto it. | 14:17 |
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| cr1901_modern | ZipCPU: You've done Verilog simulation once or twice (or 5), right? :) | 15:25 |
| ZipCPU | Yes. All with Verilator though. | 15:27 |
| ZipCPU | shapr: What board? | 15:27 |
| cr1901_modern | Well, maybe you can explain what this code is doing? https://github.com/cliffordwolf/picorv32/blob/master/picosoc/spiflash.v#L93-L96 | 15:28 |
| cr1901_modern | The comment says: "This model samples io input signals 1ns before the SPI clock edge", but I don't see how that's possible | 15:28 |
| tpb | Title: picorv32/spiflash.v at master · cliffordwolf/picorv32 · GitHub (at github.com) | 15:28 |
| shapr | ZipCPU: https://www.jamiecraig.com/novena-ice40-add-on/ | 15:28 |
| tpb | Title: Novena iCE40 Add-On | Jamie Craig (at www.jamiecraig.com) | 15:28 |
| ZipCPU | cr1901_modern: Are you building a SPI (or QSPI) controller? | 15:28 |
| * ZipCPU looks up shapr's board .. | 15:29 | |
| shapr | after reading some of the blog posts, I think maybe I need a bitstream loaded onto the xilinx chip to pass through pins or something? | 15:29 |
| cr1901_modern | ZipCPU: Neither, I want to use this core to debug something. But I want to understand how it works too :) | 15:29 |
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| ZipCPU | shapr: Does that design even have a Xilinx chip? | 15:29 |
| shapr | The novena has a ... 6 series ... spartan? | 15:30 |
| cr1901_modern | io0/1/2/3, when treated as inputs, will change at any time, typically after the previous clk edge. | 15:30 |
| cr1901_modern | I don't see how delaying by #1 ns will all of a sudden get you to "1 ns before the next SPI clock edge", | 15:30 |
| ZipCPU | Have you dug into what the flash is doing? | 15:31 |
| cr1901_modern | If anything, it looks like the model "samples 1ns after the previous SPI clock edge", not 1ns _before_ the upcoming clk edge | 15:31 |
| cr1901_modern | ZipCPU: Hmmm, I missed something (spi_action task), but Idk if it'll answer my q | 15:32 |
| * ZipCPU pulls up novena's schematic ... | 15:33 | |
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| shapr | w00 | 15:33 |
| shapr | I was hoping to have this working last night so I could do a lightning talk about it today, but instead I'm doing audience participation of bitcoin proof of work. | 15:34 |
| ZipCPU | There are *two* FPGA's on that board? Or do I have the wrong board .. ? | 15:34 |
| shapr | pretty sure there's only one | 15:34 |
| shapr | https://www.crowdsupply.com/sutajio-kosagi/novena/ | 15:35 |
| tpb | Title: Novena | Crowd Supply (at www.crowdsupply.com) | 15:35 |
| * ZipCPU must be looking at the wrong board ... | 15:35 | |
| shapr | this is the board: https://www.kosagi.com/w/index.php?title=Novena_Main_Page | 15:35 |
| tpb | Title: Novena Main Page - Studio Kousagi Wiki (at www.kosagi.com) | 15:35 |
| shapr | spartan-6 CSG324 | 15:36 |
| ZipCPU | cr1901_modern: I've done all of my SPI testing with my own (verilator-based, c++) xSPI flash simulator. | 15:36 |
| ZipCPU | It's full featured enough that I can boot my CPU off of it. | 15:36 |
| knielsen | cr1901_modern: If you sample io0_delayed at the SPI clock edge, then you (effectively) sample io0 1 second before the clock edge | 15:36 |
| knielsen | cr1901_modern: because io0_delayed is equal to the value io0 had 1 ns earlier | 15:37 |
| shapr | knielsen: oh, I use your floorplan viewer when I'm doing FPGA intro lightning talks, thanks for writing that. | 15:37 |
| knielsen | (but I didn't check in detail what the code is doing) | 15:37 |
| knielsen | shapr: glad if you found it useful! | 15:37 |
| ZipCPU | shapr: Ok, I see the S6 reference ... the board should've come with software to load it, or at least instructions on how to load it using Xilinx or some other tool ... | 15:38 |
| cr1901_modern | knielsen: Oh... ._. | 15:39 |
| shapr | ZipCPU: I suspect this is "if you have to ask, shouldn't have ordered" | 15:40 |
| cr1901_modern | ZipCPU, knielsen: thanks for both your help. I just didn't see it | 15:40 |
| shapr | oh well, I'll figure it out. | 15:40 |
| ZipCPU | shapr: Not necessarily. I've seen a lot of customers ask on the forums for well supported boards. Most often the problem is that they just don't know where to look (yet) for what they need. | 15:40 |
| shapr | I think 50-80 of these boards were produced | 15:41 |
| shapr | ah, 39 boards http://www.futureware.at/CrowdFunding/ | 15:41 |
| tpb | Title: Novena Mezzanine Board (at www.futureware.at) | 15:41 |
| ZipCPU | shapr: You need to use the "configure.sh" script from the GPBB example code. | 15:41 |
| shapr | oh, that's it? | 15:42 |
| ZipCPU | That in itself also depends upon the devmem2 program. | 15:42 |
| ZipCPU | See the instructions here: https://www.kosagi.com/w/index.php?title=FPGA_getting_started | 15:42 |
| tpb | Title: FPGA getting started - Studio Kousagi Wiki (at www.kosagi.com) | 15:42 |
| ZipCPU | Judging by the bottom of that page, it looks like you can also load bitstreams via OpenOCD over JTAG as well. | 15:43 |
| shapr | I need to send you money for consulting :-P | 15:44 |
| ZipCPU | :D | 15:44 |
| shapr | iirc, your prices are quite reasonable | 15:44 |
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| ZipCPU | Perhaps we should negotiate off forum. | 15:45 |
| shapr | Three day music festival this weekend, if not this evening, then next week. | 15:46 |
| shapr | ZipCPU: the blog posts about this board imply there isn't yet VHDL to forward the pins through the Xilinx chip | 15:47 |
| shapr | but I could be wrong, I just don't know yet | 15:47 |
| ZipCPU | Don't know ... haven't read them. | 15:50 |
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| mattvenn | quick question about doing maths with fpga | 17:48 |
| mattvenn | in c, if I have a register that's a byte in length, and some arithmetic operation happens that overflows it | 17:49 |
| mattvenn | then the maths happens correctly, and I get left with the part that fits in the reg | 17:49 |
| mattvenn | but in an fpga, say I'm doing some maths with some different width registers, | 17:49 |
| mattvenn | how do I make sure that there is enough space for the operation to happen correctly? | 17:50 |
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| mattvenn | 8 bit 10bit 10bit 2bit parameter=19 4bit parameter=16 | 17:54 |
| mattvenn | assign y_img = (y_px - y_numbers - (addr_rom * height_numbers)) + number * height_numbers; | 17:55 |
| ZipCPU | mattvenn: http://zipcpu.com/dsp/2017/07/21/bit-growth.html | 17:58 |
| tpb | Title: Bit growth in FPGA arithmetic (at zipcpu.com) | 17:58 |
| mattvenn | thanks | 18:05 |
| mattvenn | ! | 18:05 |
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