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| philtor | https://twitter.com/zipcpu/status/977516920877535232 | 15:51 |
|---|---|---|
| daveshah | I wonder if companies will change their mind once there is a full, practical bitstream flow for 7-series available.... | 15:52 |
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| awygle | https://twitter.com/c60k28/status/977567955583209472 what happened to those guys...? | 15:57 |
| daveshah | Hmmm | 15:58 |
| daveshah | https://github.com/djn3m0/debit | 15:58 |
| tpb | Title: GitHub - djn3m0/debit: Reverse-engineering tools for FPGA bitstreams, Altera and Xilinx (at github.com) | 15:58 |
| daveshah | It seems to still exist | 15:58 |
| sorear | https://www.isi.edu/sites/default/files/users/nsteiner/soni-2013-bitstream-fccm13.pdf +/unfavorable attention | 15:59 |
| sorear | haven't found details on what "unfavorable attention" constitutes | 16:00 |
| daveshah | The usual cease and desist notice, I would imagine | 16:00 |
| daveshah | I find it hard to imagine what Altera would be able to claim though | 16:01 |
| sorear | probably. I can't find any case files online for Altera and Jean-Baptiste Note or Éric Rannaud | 16:01 |
| daveshah | I highly doubt it ever got to the point of an actual case, that would certainly be heavily publicised | 16:02 |
| daveshah | Could have just been Altera threatening to remove the uni's freebies | 16:02 |
| sorear | oh that's very likely | 16:02 |
| daveshah | Altera don't mess about wrt bitstreams though - http://caselaw.findlaw.com/us-9th-circuit/1302809.html | 16:06 |
| tpb | Title: ALTERA CORPORATION v. CLEAR LOGIC INCORPORATED | FindLaw (at caselaw.findlaw.com) | 16:06 |
| awygle | Depending on how the RE is done it could violate the terms of service | 16:11 |
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| philtor | Yeah, I thought Xilinx was similarly agressive, yet we're able to generate some Xilinx7 bitstreams with yosys - what happened there? | 16:25 |
| awygle | Small point of order, Yosys can synthesize to the Xilinx primitives but not create a bitstream. That's project x-ray (have they actually generated any bitstreams yet?) | 16:29 |
| philtor | oh, I see. | 16:30 |
| philtor | So you still need Vivado to go from those primitives (blif file?) to bitstream | 16:30 |
| daveshah | I think bitstream generation is working. It's place and route that's missing - but is certainly being worked on | 16:31 |
| philtor | how do you get to bitstream without p&r? | 16:31 |
| daveshah | Manually | 16:32 |
| daveshah | A language has been developed called "FPGA assembly" | 16:32 |
| philtor | link? Google not returning anything relevant for "fpga assembly" | 16:35 |
| daveshah | https://github.com/SymbiFlow/prjxray/pull/55 | 16:35 |
| tpb | Title: FASM and xc7patch proof of concept using partial reconfig flow by kc8apf · Pull Request #55 · SymbiFlow/prjxray · GitHub (at github.com) | 16:35 |
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| daveshah | Looks like this: https://github.com/kc8apf/prjxray/blob/b6f754dae7f4f9a2f073166c66f645d68b92ce3d/minitests/partial_reconfig_flow/roi_noninv.fasm | 16:36 |
| tpb | Title: prjxray/roi_noninv.fasm at b6f754dae7f4f9a2f073166c66f645d68b92ce3d · kc8apf/prjxray · GitHub (at github.com) | 16:37 |
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| kc8apf | philtor: we've only documented CLBs and interconnect so far. We patch an existing bitstream that sets up IOBs, etc. | 17:13 |
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| ZipCPU | philtor: Thank you for your encouraging comments. | 22:08 |
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