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| nikhilp | hello | 07:48 |
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| ZipCPU | nikhilp: Please stick around next time, we like to chat but ... sometimes you need to wait a while for a response. | 11:28 |
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| philtor | So there's a bridge between GHDL and Yosys now? | 19:31 |
| philtor | https://github.com/tgingold/ghdlsynth-beta | 19:31 |
| tpb | Title: GitHub - tgingold/ghdlsynth-beta: VHDL synthesis (based on ghdl) (at github.com) | 19:31 |
| philtor | a VHDL frontend? | 19:33 |
| philtor | requires a patch to yosys source | 19:34 |
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| ZipCPU | philtor: I know there's a vhdl2verilog front end to yosys, I just don't know how well it works | 19:37 |
| philtor | This ghdlsynth looks like it would be a better path - GHDL's VHDL parser is pretty mature | 19:37 |
| philtor | Obviously, it's very beta at this point | 19:38 |
| philtor | However, it requires patching yosys source and likely the source has gotten out of sync with that patch by now | 19:39 |
| awygle | Yes, that's very exciting | 19:39 |
| philtor | The patch is fairly small, though. | 19:39 |
| * ZipCPU just doesn't get all that excited about VHDL tools ... ;P | 19:39 | |
| awygle | GHDL is GPL though, as pointed out on another channel. I wonder how that works. | 19:39 |
| philtor | tgingold should do a pull request to YosysHQ for that patch | 19:40 |
| awygle | ZipCPU: I'm excited for someone to give me a reason to learn VHDL! | 19:40 |
| ZipCPU | Run away! | 19:40 |
| ZipCPU | Fast! | 19:40 |
| daveshah | It looks like it can also be loaded as a dynamic library without needing a patch | 19:40 |
| daveshah | But I haven't investigated much | 19:40 |
| philtor | Yes, but a patch is requireed to support that | 19:40 |
| philtor | so I don't think licensing should be an issue | 19:41 |
| philtor | In fact, the patch appears to only be to the yosys Makefile | 19:41 |
| philtor | yes, that seems to be the only thing being patched. | 19:42 |
| philtor | Good separation between the two projects | 19:42 |
| philtor | no licencing issues | 19:42 |
| philtor | looks a lot like the verific bridge | 19:43 |
| philtor | Pretty cool, but needs work. | 19:44 |
| philtor | Fortunately, the only code in the bridge is in C++ | 19:44 |
| philtor | so you don't need to learn Ada | 19:44 |
| philtor | to contribute | 19:44 |
| daveshah | Looks like the dynamic library does work without the patch using the Yosys module system - but I agree the patch is a much nicer approach | 19:45 |
| daveshah | AFAIK a lot of the work is being done by the `synth` part of ghdl which is in Ada, I don't know how complete that bit is | 19:46 |
| daveshah | https://github.com/ghdl/ghdl/tree/master/src/synth | 19:46 |
| tpb | Title: ghdl/src/synth at master · ghdl/ghdl · GitHub (at github.com) | 19:46 |
| philtor | ah, right. It's actually in the GHDL codebase already. | 20:04 |
| * shapr hops cheerfully | 20:07 | |
| shapr | vacation is GREAT! | 20:07 |
| ZipCPU | At the last robotics competition, they asked what a robot's favorite type of music. The FROGbots team replied "Hip hop", although the answer for all the other robots was "Heavy metal" | 20:10 |
| shapr | bwahahaha | 20:11 |
| shapr | ZipCPU: twitter worthy for sure | 20:11 |
| ZipCPU | Here's a question for those with experience using the concurrent assertions that yosys (without verific) doesn't (yet) support ... | 20:51 |
| ZipCPU | What's the "killer app" that makes such assertions valuable? | 20:51 |
| ZipCPU | What's the "killer app" that makes such *concurrent* assertions valuable? | 21:01 |
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| ZipCPU | Hmm ... assertions for a UART: 117 lines without concurrent assertions, 47 lines with ... | 21:57 |
| ZipCPU | ... wonder what the difference would be for a SPI flash ... ? | 21:58 |
| sorear | can concurrent assertions always be replaced with regular assertions? | 22:02 |
| awygle | ZipCPU: all i want in the world is for a notion of a "property" as a first class object | 22:02 |
| ZipCPU | sorear: I think the right way to answer your question would be to start with: there are two types of assertions (or assumptions) concurrent and immediate. | 22:03 |
| ZipCPU | yosys currently only supports the immediate assumptions. | 22:03 |
| ZipCPU | concurrent assumptions include the System Verilog sequence/property language subset. | 22:04 |
| cr1901_modern | ? "assert property" is a concurrent assertion. | 22:04 |
| cr1901_modern | yosys supports that, it just doesn't support anything else :P | 22:04 |
| awygle | yosys only supports that in a trivial way, and does so by converting it to the implied immediate version, iirc | 22:04 |
| cr1901_modern | http://www.clifford.at/papers/2016/yosys-smtbmc/slides.pdf slide 11, awygle is correct. And I even read this presentation multiple times :( | 22:07 |
| ZipCPU | cr1901_modern: Yosys does not support: assert property (A |-> B ##1 C [*3:8] ##1 !B); as an example. | 22:08 |
| * awygle prints out "awygle is correct", frames it, adds it to a wall of dozens of similar frames | 22:08 | |
| cr1901_modern | Well idk if yosys supports ##, but it certainly doesn't support |-> | 22:08 |
| cr1901_modern | last I checked* | 22:09 |
| awygle | i just want to be able to do "assert property(acks_are_happy)" and define what happiness means to acks somewhere else | 22:09 |
| * ZipCPU signs awygle's printout | 22:09 | |
| cr1901_modern | Also, obligatory link. Have fun! https://stackoverflow.com/questions/24912264/systemverilog-implies-operator-vs | 22:09 |
| tpb | Title: system verilog - SystemVerilog: implies operator vs. |-> - Stack Overflow (at stackoverflow.com) | 22:09 |
| awygle | otherwise it feels like an SLA principle violation | 22:10 |
| awygle | but it's possible i could solve this problem with functions if i knew verilog better | 22:10 |
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