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| ZipCPU | So ... I spent today trying to understand system verilog's concurrent assertion language. | 02:18 |
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| ZipCPU | Now I think Clifford gave us a gift by *not* including it in yosys. | 02:18 |
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| awygle | ZipCPU: oh? do tell | 04:07 |
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| ZipCPU | awygle: https://gist.github.com/ZipCPU/6ae69cc05e13e412d0389d11685f7a70 | 15:01 |
| tpb | Title: gist:6ae69cc05e13e412d0389d11685f7a70 ยท GitHub (at gist.github.com) | 15:01 |
| ZipCPU | awygle: Those are some wishbone bus properties in the concurrent assertion subset of System Verilog. | 15:02 |
| ZipCPU | While I like the language for its expressive ability, it's ... not nearly as easy to read and comprehend. | 15:02 |
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| cr1901_modern | awygle: You read this and reconsider your life choices https://www.doulos.com/knowhow/sysverilog/tutorial/assertions/ | 17:22 |
| tpb | Title: SystemVerilog Assertions Tutorial (at www.doulos.com) | 17:22 |
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| cr1901_modern | Oh right this was the other reference I used: http://www.sutherland-hdl.com/papers/2006-DesignCon_Getting_Started_with_SVA_presentation.pdf | 17:30 |
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| ZipCPU | cr1901_modern: Yeah, I was referencing that tutorial a *lot* yesterday. | 18:34 |
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