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| ZipCPU | Hey, this is cool! Building an RGMII network interface. Last time I did this, I had to iterate over many painful rounds with the simulator. This time, I think I got it right with less than one bug found in the network code. | 04:12 |
|---|---|---|
| ZipCPU | (Other bugs were found in the bus addressing, etc.) | 04:13 |
| ZipCPU | The difference? This time I formally proved all of th network sub-components: add a CRC, add a hardware MAC, add a preamble, insure a minimum packet length, and then the inverse on the receive. | 04:13 |
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| awygle | ZipCPU: nice! | 04:29 |
| ZipCPU | ;) The last time it was an RMII interface, but still ... I had to rebuild the whole thing to operate on 8-bits at a time instead of 4. | 04:29 |
| awygle | my actual job has been throttled to 11, i look forward to getting back to personal projects... | 04:31 |
| awygle | i think i've come up with a way to prove the fifo that i find aesthetically superior to breaking out the internal pointers | 04:32 |
| ZipCPU | Yeah, I understand comppletely about the job. | 04:33 |
| ZipCPU | As for the FIFO, I'd love to see it ... but I'll be glad to wait until you either get it working or get stuck. | 04:33 |
| awygle | i'll be sure to show you when i get there :) | 04:33 |
| awygle | it may be somewhat ridiculous to stress out over these kinds of things, but i'm much more interested in developing an approach than a formally verified fifo in particular | 04:34 |
| awygle | can you share anything about the project which has you developing an RGMII core? | 04:38 |
| ZipCPU | Sure! Most of the code is on line at https://github.com/ZipCPU/videozip although I haven't yet checked in all of the ethernet components. | 04:40 |
| tpb | Title: GitHub - ZipCPU/videozip: A ZipCPU SoC for the Nexys Video board supporting video functionality (at github.com) | 04:41 |
| ZipCPU | The ethernet components themselves are coming from my OpenArty project, at https://github.com/ZipCPU/openarty | 04:41 |
| tpb | Title: GitHub - ZipCPU/openarty: An Open Source configuration of the Arty platform (at github.com) | 04:41 |
| ZipCPU | Only thing is .... they need to be modified from RMII to RGMII, and I took the opportunity to add formal proofs along the way. | 04:42 |
| ZipCPU | (To be posted ...) | 04:42 |
| awygle | very interesting! thanks | 04:44 |
| awygle | (this bot is kind of weird thoughj) | 04:44 |
| ZipCPU | Yeah .... not sure I like it. | 04:44 |
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| mattvenn_ | I got my i2c master workiong with the new sensor | 08:57 |
| mattvenn_ | I made 3 changes: repeated starts, more setup/hold time consideration and learnt something new that was really important | 08:58 |
| mattvenn_ | master shoudl nack the slave on the last data packet when reading | 08:58 |
| mattvenn_ | it's in the spec but it hadn't mattered on previous sensors. This one actually followed the spec and kept the sda line down without the final nack from the master | 08:59 |
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| mattvenn_ | this is a useful guide to the spec: https://www.nxp.com/docs/en/user-guide/UM10204.pdf | 09:44 |
| mattvenn_ | and this one has very clear pictures to show who should control SDA when: http://www.ti.com/lit/an/slva704/slva704.pdf | 09:44 |
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| ZipCPU | mattvenn_: I2C master for an iCE40? How many LUT4's? | 12:31 |
| mattvenn_ | 295 | 12:32 |
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| ZipCPU | Ahh, ok, got it ... my I2C master must need some serious work then. | 12:54 |
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| mattvenn_ | mine still doesn't handle nacks from slaves or clock stretching | 13:02 |
| ZipCPU | Oh, well ... that is a difference. Mine handles both. How does yours handle losing a bus arbitration battle? | 13:15 |
| mattvenn_ | single master only | 13:16 |
| mattvenn_ | to this day I've still never used a multimaster i2c bus | 13:16 |
| ZipCPU | Well, .. there's another difference then. You consider that you *own* the bus. Must make things nice. ;) | 13:16 |
| mattvenn_ | yep! | 13:20 |
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| awygle | I recommend avoiding multi master I2C if at all possible | 16:12 |
| ZipCPU | awygle: Yeah, sure, but ... it's the protocol. | 16:13 |
| awygle | Sure, and sometimes you can't avoid it. But it's a bad protocol, and sometimes you can :-P | 16:21 |
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| mattvenn_ | take a look at page 8 of https://www.nxp.com/docs/en/user-guide/UM10204.pdf | 16:36 |
| mattvenn_ | useful table for what is required for fulfilling different parts of the spec | 16:36 |
| mattvenn_ | my module supports all mandatory requirements of single master | 16:37 |
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