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| mithro | digshadow: https://www.irccloud.com/pastebin/W0HxAm6V/ | 04:04 |
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| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 04:04 |
| mithro | daveshah/ jhol: ^ | 04:04 |
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| mithro | https://www.irccloud.com/pastebin/f7pHOt17/ | 04:46 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 04:46 |
| mithro | Need to fix the tile type... | 04:47 |
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| mithro | morning everyone | 17:17 |
| mithro | kem_: ping? | 17:17 |
| mithro | jhol: ping? | 17:17 |
| mithro | daveshah: ping? :-P | 17:17 |
| mithro | kem_: Had a chance to look at the pass_gate stuff at all? | 17:18 |
| daveshah | mithro: hi | 17:26 |
| mithro | daveshah: How goes things? | 17:26 |
| mithro | daveshah: It would be good to get someone else to start reproducing the ice40 stuff | 17:26 |
| daveshah | mithro: yes, can try and take a look tomorrow | 17:27 |
| mithro | daveshah: That would be good | 17:27 |
| daveshah | It looks like you're having trouble getting names for some things? | 17:27 |
| mithro | daveshah: Not hugely | 17:28 |
| mithro | daveshah: I was having issues with invalid route existing | 17:29 |
| daveshah | I see | 17:29 |
| daveshah | What was the pass_gate stuff? | 17:31 |
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| jhol | mithro: hi! | 19:46 |
| mithro | jhol: Hi! - I've been working on the HLC output | 19:46 |
| jhol | yeah - I saw you making progress | 19:46 |
| mithro | jhol: I had a bunch of questions | 19:49 |
| jhol | sure - go right ahead! | 19:49 |
| mithro | jhol: Why were you flipping the y coordinates? | 19:49 |
| jhol | because of you ice40 coordinate diagram vs. the diagram in icestorm | 19:49 |
| mithro | jhol: Oh? | 19:50 |
| mithro | jhol: which diagram? | 19:50 |
| jhol | http://www.clifford.at/icestorm/bitdocs-1k/ | 19:50 |
| tpb | Title: Project IceStorm iCE40 HX1K Overview (at www.clifford.at) | 19:50 |
| jhol | your diagram is bottom-up IIRC | 19:50 |
| jhol | and I think VPR is bottom-up in general, right? | 19:51 |
| mithro | jhol: That diagram is bottom up as well? | 19:51 |
| jhol | ugh you're right | 19:51 |
| jhol | ok... that's a mistake | 19:51 |
| mithro | okay | 19:52 |
| mithro | jhol: I was wondering why _write_hlc_pin_name is so complicated? | 19:54 |
| jhol | well it's a kind of hack | 19:56 |
| jhol | but basically I'm using the pin-type prefix information to control the wire traversal that the code uses | 19:56 |
| mithro | jhol: Shouldn't it just be able to use the names in the pb_type ? | 19:56 |
| jhol | well you have to make them exactly match icebox | 19:57 |
| jhol | which isn't always easy | 19:57 |
| jhol | it works if you look at the naming in the tile-routing-pb | 19:57 |
| mithro | tile or top? | 19:57 |
| jhol | tile - I did all my development with tile | 19:58 |
| jhol | http://www.clifford.at/icestorm/bitdocs-1k/tile_8_16.html | 19:58 |
| tpb | Title: Project IceStorm iCE40 HX1K LOGIC Tile (8 16) (at www.clifford.at) | 19:58 |
| jhol | if you look at some of the net names, it's quite tricky to convert the naming so that it consistently matches icebox | 19:59 |
| jhol | local_g3_{0,1,2,3,4,5,6,7} being an example | 19:59 |
| jhol | lutff_{0,1,2,3,4,5,6,7}/in_2 being another | 19:59 |
| jhol | so I somewhat abused the block-type prefixes so it kinda works | 19:59 |
| mithro | - lutff_{0,1,2,3,4,5,6,7}_in[2] | 20:00 |
| mithro | or? | 20:00 |
| mithro | lutf[0].in[2] ? | 20:00 |
| jhol | well in icebox it's lutff_0_in2 | 20:00 |
| jhol | in VPR it's going to be something like BEL-??_LUTFF.in[2] | 20:01 |
| jhol | -- or whatever it was | 20:01 |
| jhol | sorry - it's "lutff_0/in2" in icebox | 20:02 |
| jhol | the bad thing about this hacky conversion is that it's hacky | 20:03 |
| jhol | the good thing is that I didn't have to write any conversion tables in C++ | 20:03 |
| jhol | by setting up the block and pin names in the XML just right, it's possible to translate the nomenclature to the correct icebox format | 20:04 |
| mithro | jhol: Yeah, the idea is that you set up the block/pin names correctly and the code shouldn't need to know anything special about the icebox names? | 20:05 |
| jhol | exactly, but the problem is that there's a bit of a rift to bridge | 20:06 |
| jhol | so in the symbiflow arch-defs, because of VPR design issues, the cells are a bit convoluted | 20:06 |
| jhol | in the real world, each tile has 8 cells containing 1x LUTFF and 1x DFF | 20:07 |
| mithro | jhol: The idea behind these functions -> https://github.com/mithro/vtr-verilog-to-routing/blob/fasm/vpr/src/util/fasm.cpp#L116-L155 | 20:07 |
| tpb | Title: vtr-verilog-to-routing/fasm.cpp at fasm · mithro/vtr-verilog-to-routing · GitHub (at github.com) | 20:07 |
| jhol | sorry: 1x LUT and 1x DFF | 20:07 |
| jhol | but in symbiflow-arch-defs there's 1 set of 8-cells for the LUTs and then a <mode> wrapper containing 8-DFFs | 20:08 |
| jhol | and it has to be this way because the FFs stay constant regardless of DFF modes | 20:08 |
| jhol | so the XML contains a lot of extraneous pb_types, pins and direct links that are needed just to represent the ice40 in a way that make VPR not crash | 20:09 |
| jhol | so the HLC code I wrote skips over fake things until it encounters things that are annotated in such as way as to indicate that they represent something real | 20:10 |
| mithro | jhol: Yeah - that is why there are BLK_IG | 20:14 |
| jhol | yes, that one came in handy | 20:15 |
| jhol | I abused some of the other type name prefixes | 20:15 |
| jhol | -- I recomend you play with the tile-routing version to see it in action. you will see it generating something reasonable | 20:16 |
| mithro | jhol: It would be good to get you to repo some of the stuff I have done | 20:16 |
| jhol | sure | 20:16 |
| jhol | though it mgiht be a while before I get to it | 20:16 |
| jhol | do you have a HLC file from arachne-pnr to compare your output to? | 20:17 |
| mithro | yes | 20:20 |
| jhol | cool ok | 20:21 |
| mithro | auto &element_lines = (*elements_.insert( | 20:26 |
| mithro | std::make_pair(std::to_string(cell), std::vector<std::string>())).first).second; | 20:26 |
| mithro | jhol: Why is this a cell + vector of strings? | 20:27 |
| jhol | so if you look at the HLC format, it wraps the cell config in an inner set of curly brackets | 20:28 |
| jhol | it's probably just about possible to write out the cells in 1-pass, but I wasn't sure that would be the case, so I put the element lines into this table which gets written out in close_tile() | 20:30 |
| jhol | not that std::map::insert means insert_new_element_or_return_existing_element | 20:30 |
| jhol | *note that... | 20:31 |
| mithro | jhol: What is "collect_chain" about? | 20:41 |
| jhol | very simple c++ ;) | 20:41 |
| jhol | so basically... | 20:42 |
| jhol | in visit_all_impl -> process_ports -> process_route, we make a big list of links between nodes in the cell | 20:43 |
| jhol | collect_chain starts at a pin and iterates down or up the chain of links until it gets to the end of a chain of links | 20:45 |
| jhol | it is written in with that convoluted C++ because it can go down or up the links, and I didn't want to copy-paste code | 20:45 |
| jhol | it iterates a long a chain of links greedily making chains, and removing any links from the the list so they are no restated later | 20:46 |
| jhol | so for example, the links_ table will have some random connections: C->E C->D A->B B->C | 20:47 |
| jhol | collect_chain will with the argument of tip=D and up=true, A->B->C->D | 20:47 |
| jhol | then on the second with tip=E and up=true, it will return a chain C->E | 20:48 |
| jhol | this is useful because in HLC you can write a chain of multiple links on one line | 20:49 |
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