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mithro | digshadow: Don't forget https://docs.google.com/document/d/1kTehDgse8GA2af5HoQ9Ntr41uNL_NJ43CjA32DofK8E/edit#heading=h.qwbbqhhq91qi exists... | 19:33 |
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tpb | Title: VPR and iCE40 Information - Google Docs (at docs.google.com) | 19:33 |
digshadow | roger | 19:35 |
mithro | digshadow: https://docs.google.com/drawings/d/1tyuFQk9B8oEcdbSt7T_SyF8HAPLPh84Q-k6NIDQxOvo/edit | 19:40 |
tpb | Title: iCE4 - iCE40 with only 4x4 tiles - Google Drawings (at docs.google.com) | 19:40 |
mithro | digshadow: FYI - It might be worth looking at kmurry's comment here -> https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/335#issuecomment-385406926 | 20:40 |
tpb | Title: rr_graph reader: review unexpected channel direction edges · Issue #335 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 20:40 |
digshadow | yeah saw that | 20:41 |
digshadow | reminds me, also I don't think we tried empty channels yet | 20:41 |
digshadow | to see if that works for aesthetic purposes. or did you say you tried that and it crashes | 20:42 |
mithro | digshadow: I thought it crashed - but worth checking... | 20:42 |
digshadow | could add a dummy unroutable channel | 20:46 |
mithro | digshadow: That is what I was thinking of trying... | 20:46 |
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digshadow | mithro: fyi that performance issue I mentioned earlier, is resolved. Caused by a pin ptc brute force lookup where it should have been using the index (which you already had there) | 23:04 |
mithro | digshadow: Great! | 23:09 |
digshadow | mithro: https://github.com/SymbiFlow/symbiflow-arch-defs/issues/104 | 23:11 |
digshadow | request for comment | 23:11 |
tpb | Title: rr_graph import: clean up pin import · Issue #104 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 23:11 |
digshadow | low priority right now though | 23:12 |
mithro | I don't really understand the issue -- lets discuss it later | 23:13 |
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