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| mithro | kem_: I think I've found a weird bug in the rr_graph generation stuff - trying to produce a minimal test case to understand what is going on | 19:15 |
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| mithro | https://www.irccloud.com/pastebin/KPd6SjE2/ | 19:16 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 19:16 |
| mithro | It very much looks like the edges are getting connected to the wrong nodes -- I'm seeing the same thing in the rr_graph.echo file... | 19:38 |
| kem_ | Getting to a MWE is the right approach | 20:27 |
| kem_ | I assume this is for an RR graph that VPR built? | 20:27 |
| mithro | kem_: Yeah | 20:39 |
| mithro | kem_: I'm trying to make sure I just haven't done something really stupid in my architecture file | 20:39 |
| mithro | kem_: I have been working on a Python library for manipulating rr_graphs | 20:41 |
| kem_ | mithro: Makes a lot of sense! | 20:42 |
| mithro | kem_: If you want a distraction, I could explain how to build my architecture files | 20:44 |
| kem_ | mithro: Perhaps not at the moment, but definitely in the future! Last time I looked at one it was somewhat difficult to follow, so understanding how they are put together would likely help :) | 20:48 |
| mithro | kem_: Sure, I have a bunch of much simpler "test" architectures now | 20:49 |
| mithro | kem_: Welp - hit a different bug now... | 21:50 |
| mithro | kem_: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/310 | 21:50 |
| tpb | Title: Segfault in alloc_and_load_track_top_pin_lookup · Issue #310 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 21:50 |
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