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| mithro | CarlFK: The wiki at https://github.com/timvideos/HDMI2USB/wiki is probably going away sometime soonish | 00:40 |
|---|---|---|
| tpb | Title: Home · timvideos/HDMI2USB Wiki · GitHub (at github.com) | 00:40 |
| mithro | CarlFK: I think you might care about https://github.com/timvideos/HDMI2USB/wiki/Flashing-Firmware or https://github.com/timvideos/HDMI2USB/wiki/Flashing-Opsis-on-Xenial ? | 00:41 |
| tpb | Title: Flashing Firmware · timvideos/HDMI2USB Wiki · GitHub (at github.com) | 00:41 |
| CarlFK | mithro: the flashing page is used pretty often , so it needs to live somewhere | 00:42 |
| mithro | CarlFK: I've cleaned out a lot of the rest of that page | 00:42 |
| mithro | s/page/wiki | 00:42 |
| cr1901_modern | tinyfpga: wishbone slave is the normal way | 00:42 |
| mithro | CarlFK: Which one are you using? | 00:42 |
| CarlFK | mithro: https://github.com/timvideos/HDMI2USB/wiki/Flashing-Firmware | 00:43 |
| tpb | Title: Flashing Firmware · timvideos/HDMI2USB Wiki · GitHub (at github.com) | 00:43 |
| tinyfpga | mithro: I want to instantiate a specific RAM module | 00:43 |
| mithro | tinyfpga: You mean a specific RAM black box? | 00:43 |
| tinyfpga | mithro: I almost have it working....implementing a wb slave like cr1901_modern suggestes | 00:43 |
| tinyfpga | mithro: correct | 00:44 |
| mithro | CarlFK: Shall we delete the other? | 00:44 |
| CarlFK | mithro: yes | 00:44 |
| mithro | CarlFK: done | 00:45 |
| CarlFK | mithro: as long as you are looking at that page, maybe you know if I can do this: check box that hides/unhide sections - but I think I need .js - like any of the [x]ShowMore tic boxes here: https://veyepar.nextdayvideo.com/main/schedule/410/E/14193/ | 00:49 |
| tpb | Title: veyepar: Welcome to CircuitPython! (at veyepar.nextdayvideo.com) | 00:49 |
| cr1901_modern | tinyfpga: If you are using litex you also need to make a call to add_memory_region for wishbone-based devices to show up in your C defines | 00:49 |
| cr1901_modern | s/litex/litex.soc/ | 00:50 |
| cr1901_modern | Or you can call register_mem which will add the FPGA connections _and_ create the C defines | 00:51 |
| tinyfpga | cr1901_modern: I’m using register_mem | 01:03 |
| cr1901_modern | How many FPGA devs does it take to debug a single board? | 01:05 |
| mithro | Well, the README at https://github.com/timvideos/litex-buildenv should now make a lot more sense... | 01:23 |
| tpb | Title: GitHub - timvideos/litex-buildenv: An environment for building LiteX based FPGA designs. Makes it easy to get everything you need! (at github.com) | 01:23 |
| mithro | Looks like conda is down :-( | 01:32 |
| xobs | tinyfpga: I just woke up, but did you get your litex stuff working? | 01:39 |
| tinyfpga | xobs: working through it, I just got some custom SRAM black boxes working on the wishbone bus | 01:42 |
| cr1901_modern | If you get an lm32 working with spiflash on tinyfpga on your first try, I'm going to eat my mattress | 01:42 |
| xobs | I have a super barebones first draft attempt at a ws2812b spec catcher. It uses the PLL, and is at https://github.com/xobs/ws2812b-catcher/blob/master/ws2812b-catcher.py' | 01:43 |
| tinyfpga | cr1901_modern: I’m just using the UART wishbone bridge for now | 01:43 |
| tinyfpga | xobs: I get a 404 when I try to access that page | 01:43 |
| xobs | It also uses my lxbuildenv environment. But that might be less interesting if you've already got everything set up. | 01:43 |
| xobs | https://github.com/xobs/ws2812b-catcher/blob/master/ws2812b-catcher.py (no trailing apostrophe?) | 01:44 |
| tpb | Title: ws2812b-catcher/ws2812b-catcher.py at master · xobs/ws2812b-catcher · GitHub (at github.com) | 01:44 |
| tinyfpga | cr1901_modern: what SPI core are you using to get memory-mapped SPI access? | 01:44 |
| xobs | The pll values come from the output of "icepll" | 01:44 |
| tinyfpga | xobs: nice...but why do you call it “Spec Catcher”? | 01:45 |
| cr1901_modern | litex.soc.cores.spi_flash | 01:45 |
| tinyfpga | xobs: I’m not familiar with that term | 01:45 |
| tinyfpga | cr1901_modern: so I should be able to put that on the wishbone bus as a slave and access it over the UART bridge, I might just give that a try next | 01:46 |
| cr1901_modern | Sure, that'll work. | 01:46 |
| xobs | tinyfpga: It's the start of a project. We received a batch of ws2812b chips from the manufacturer that would output an out-of-spec signal even when you fed an in-spec signal in. The idea was to use a ws2812b to sweep good signals in and make sure good timing signals come out. | 01:46 |
| cr1901_modern | The problem w/ my generated SoCs based on traces is: PC and branch control gets corrupted | 01:47 |
| mithro | Anyone used https://direnv.net/ | 01:48 |
| tpb | Title: direnv - unclutter your .profile (at direnv.net) | 01:48 |
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| cr1901_modern | Nah, I just manually update all my .profiles | 01:54 |
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| cr1901_modern | though I'm prob gonna start using a .bash_aliases file soon | 01:55 |
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| cr1901_modern | mithro: I think the "minimal" lm32 variant should be altered to have: multiplier/divider/multishift disabled. And a "lite" variant is "the current min, except with 2kB icache". Would you object if I made those changes? | 02:03 |
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| mithro | cr1901_modern: Nope | 02:03 |
| cr1901_modern | Cool, thanks | 02:03 |
| cr1901_modern | And this will finally let me get rid of those awful hacks I have in my fork of tinyfpga-soc | 02:04 |
| mithro | cr1901_modern: Did you ever see https://github.com/mithro/litex/pull/2 ? | 02:04 |
| tpb | Title: WIP - Make CPUs more configurable by mithro · Pull Request #2 · mithro/litex · GitHub (at github.com) | 02:04 |
| cr1901_modern | I have not, will take a look | 02:04 |
| cr1901_modern | tinyfpga: If you've seen _florent_'s tinyfpga-soc, I'll be uploading mine soon. Mine is technically a fork, but has significantly diverged from _florent_'s while I test/break stuff | 02:05 |
| cr1901_modern | So you may wish to clone it/treat it as a totally separate repo :) | 02:05 |
| mithro | cr1901_modern: The aim with that pull request was to do proper CPU configurations | 02:05 |
| mithro | cr1901_modern: I was trying to put together a minimal or1k at that time too I think.... | 02:06 |
| cr1901_modern | Oh I do think I remember this PR | 02:06 |
| cr1901_modern | what is the @property decorator? | 02:07 |
| cr1901_modern | xobs: Is vexriscv still borked due to the bad underscore in the filename? | 02:08 |
| mithro | cr1901_modern: https://www.programiz.com/python-programming/property | 02:11 |
| tpb | Title: Python @property: How to Use it and Why? - Programiz (at www.programiz.com) | 02:11 |
| tinyfpga | cr1901_modern: ok, I’m using that same soc for the start of another project, so it should be at least a little familiar to me | 02:13 |
| xobs | cr1901_modern: Yeah. You can prove that by doing: wget 'https://raw.githubusercontent.com/m-labs/VexRiscv-verilog/master/VexRiscv-MinDebug.v'; yosys -p 'read_verilog VexRiscv-MinDebug.v' > /dev/null | 02:14 |
| cr1901_modern | tinyfpga: Cool. I like lm32 b/c internally it's easy to read and not written in "FP wrapper over Verilog" lang :P | 02:25 |
| cr1901_modern | xobs: Alright, I'll test this. Phew... gonna be a busy few hours | 02:26 |
| tinyfpga | cr1901_modern: so i integrated the SPI flash core into my soc | 02:28 |
| tinyfpga | cr1901_modern: and I’m using the bridge to read data off of SPI flash | 02:28 |
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| tinyfpga | cr1901_modern: I’m reading from address zero | 02:28 |
| tinyfpga | cr1901_modern: and the data I receive does not match what I expect to get | 02:29 |
| cr1901_modern | mithro: My opinion re: pull #2 in Litex is "let's sort out the current hardcoded min/lite/normal variants we have right now, which should be fine for most use cases, and revisit adding custom configs on top of the hardcoded variants using pull #2." | 02:29 |
| cr1901_modern | tinyfpga: "icesleep -s"? | 02:29 |
| tinyfpga | cr1901_modern: icepack -s | 02:29 |
| mithro | tinyfpga: https://docs.google.com/document/d/1J8gmL6sasN8b3gZHkUw03gIBYeeteWHtUmERV75vI54/edit | 02:29 |
| tpb | Title: MiSoC / LiteX "CPU Configs" - Google Docs (at docs.google.com) | 02:29 |
| mithro | opps | 02:29 |
| mithro | cr1901_modern: https://docs.google.com/document/d/1J8gmL6sasN8b3gZHkUw03gIBYeeteWHtUmERV75vI54/edit - I listed a bunch of "CPU Configs" I thought should exist in that doc | 02:30 |
| tpb | Title: MiSoC / LiteX "CPU Configs" - Google Docs (at docs.google.com) | 02:30 |
| * mithro goes to move that into the LiteX BuildEnv wiki | 02:31 | |
| cr1901_modern | tinyfpga: Yes, that. Hmmm... | 02:31 |
| tinyfpga | cr1901_modern: im wondering if this is related to your issue | 02:31 |
| tinyfpga | cr1901_modern: I’m going to investigate further | 02:31 |
| cr1901_modern | tinyfpga: Well, it's possible I didn't test this | 02:32 |
| cr1901_modern | Although I'm pretty sure I did at some point | 02:32 |
| cr1901_modern | tinyfpga: In any case, I welcome alternate approaches to debugging that I didn't think of, even if they should've been obvious in retrospect | 02:33 |
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| cr1901_modern | I was mainly focusing on what came _out_ of the SPI flash, not what the CPU "sees" | 02:33 |
| tinyfpga | cr1901_modern: what value are you passing into SpiFlash for “dummy”? | 02:34 |
| cr1901_modern | the default | 02:34 |
| tinyfpga | cr1901_modern: I believe it should be “8”, the default is way off | 02:34 |
| cr1901_modern | If you try it and it works, I'll send you a photo of me eating my mattress | 02:35 |
| tinyfpga | cr1901_modern: i set it to 8 just now and the data matches what I expected to see | 02:35 |
| tinyfpga | cr1901_modern: that parameter is the number of dummy bits between the SPI command+address and the beginning of the data | 02:35 |
| cr1901_modern | But the traces I saw show the correct data come out of the chip | 02:36 |
| tinyfpga | cr1901_modern: it’s 8 SPI clocks on the Adesto parts (and most SPI flash chips as far as I know) | 02:36 |
| tinyfpga | cr1901_modern: the correct data will still come out of the chip, but the SpiFlash core will interpret it incorrectly | 02:36 |
| cr1901_modern | Hmmmm | 02:37 |
| * cr1901_modern believes you, just trying to parse it | 02:37 | |
| cr1901_modern | mithro: Re: https://docs.google.com/document/d/1J8gmL6sasN8b3gZHkUw03gIBYeeteWHtUmERV75vI54, I think you showed me this doc a few days ago? | 02:37 |
| cr1901_modern | I prefer the current terminology "lite", "min", and "" | 02:38 |
| tinyfpga | cr1901_modern: that parameter just tells the core how many clocks to wait before shifting in the data, the default waits 15 clocks so it will drop the first 7 bits of actual data | 02:38 |
| cr1901_modern | where "" is default and "full" | 02:38 |
| tinyfpga | cr1901_modern: you can just post the photo here when you’re ready XD | 02:38 |
| cr1901_modern | My God... and I missed that all the time | 02:38 |
| cr1901_modern | mithro: where "" is default and corresponds to what I would call "full", i.e. "Performance" on your chart. | 02:40 |
| cr1901_modern | But this is a bikeshed we can talk about in a bit | 02:40 |
| cr1901_modern | I'm going to test now and see what happens | 02:42 |
| cr1901_modern | tinyfpga: For the record, it is still possible for me to crash tinyfpga w/ lm32 without spiflash, but only w/ arachne-pnr and only with certain I/O removed | 02:50 |
| cr1901_modern | the same design w/ nextpnr succeeds, so it could be arachne weirdness | 02:50 |
| cr1901_modern | tinyfpga: it worked | 02:57 |
| cr1901_modern | I owe you a photo | 02:57 |
| cr1901_modern | Next time I strip my bed I'll take it | 02:57 |
| tinyfpga | cr1901_modern: woohoo!! | 02:59 |
| mithro | cr1901_modern: What was the problem in the end? | 03:03 |
| cr1901_modern | mithro: dummy in the SPIFlash core wasn't set properly | 03:04 |
| mithro | cr1901_modern: Oh | 03:04 |
| cr1901_modern | mithro: So you and tinyfpga were right all along- the SPIflash core was badly configured. I didn't think to check the boundary between the SPIflash and CPU | 03:05 |
| mithro | cr1901_modern: Hrm? I would have thought to try reading the spiflash data using the wishbone bridge? | 03:05 |
| cr1901_modern | mithro: Because I saw LA traces that showed the correct data coming into the chip, I didn't think to attach a wishbone bridge. | 03:06 |
| cr1901_modern | I figured that something was going wrong inside the CPU and swapping it out for a bridge wouldn't tell me anything | 03:07 |
| cr1901_modern | cc: daveshah... this probably means that spiflash boot will work on your 5k board too | 03:11 |
| cr1901_modern | The BIOS works as well | 03:21 |
| mithro | CarlFK: https://travis-ci.org/timvideos/HDMI2USB-litex-firmware/builds/423491972 - The build is slowly looking more green | 03:24 |
| CarlFK | mithro: yay. that's a lot of red still | 03:25 |
| mithro | CarlFK: Your build matrix was set to allow the failure of jobs 1112.25, 1112.26, and 1112.27. | 03:25 |
| mithro | CarlFK: so, only one which is causing issues is 1112.21 | 03:26 |
| mithro | CarlFK: It should also no longer be blocking the hdmi2usb builds | 03:26 |
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| cr1901_modern | tinyfpga: How does the "-i" switch to tinyprog work? | 03:44 |
| cr1901_modern | Does it match against the "name" JSON entry? | 03:44 |
| cr1901_modern | or the UUID? | 03:44 |
| tinyfpga | cr1901_modern: it uses the uuid, you only need to use the first few characters | 03:45 |
| cr1901_modern | Is there any way to tell tinyfpga to program based on name (in case you have multiple boards that are tinyprog compatible attached)? | 03:46 |
| cr1901_modern | s/tinyfpga/tinyprog/ | 03:47 |
| tinyfpga | cr1901_modern: not currently...is the idea to batch program multiple boards at once? | 03:47 |
| cr1901_modern | No... the idea is that "tinyprog should be considered a generic programmer class in Migen/LiteX, but we need a way to tie the programmer to a specific board each time we construct an instance" | 03:50 |
| cr1901_modern | so a "tinyprog" class instance meant for say, Arty, doesn't accidentally try looking for (or programming!) a BX board | 03:50 |
| cr1901_modern | tinyfpga ^^ | 03:52 |
| tinyfpga | cr1901_modern: I see, yes, that’s an option I can add | 04:00 |
| tinyfpga | cr1901_modern: maybe -t/—type or -n/—name | 04:01 |
| tinyfpga | cr1901_modern: file an issue on the TinyFPGA-Bootloader repo | 04:01 |
| cr1901_modern | ack | 04:01 |
| mithro | https://github.com/timvideos/litex-buildenv/wiki/Images | 04:14 |
| tpb | Title: Images · timvideos/litex-buildenv Wiki · GitHub (at github.com) | 04:14 |
| cr1901_modern | tinyfpga: https://github.com/tinyfpga/TinyFPGA-Bootloader/issues/20 | 04:31 |
| tpb | Title: Add `name` option to `tinyprog` · Issue #20 · tinyfpga/TinyFPGA-Bootloader · GitHub (at github.com) | 04:31 |
| benreynwar | mithro: I've had a look at cocotb in the past, but have been put off by the fact that the standard way to write a test involves Makefiles. What is timvideos using for unit testing? | 04:38 |
| mithro | benreynwar: I like that you think we have unit testing :-P | 04:38 |
| benreynwar | mithro: Ha! | 04:38 |
| mithro | benreynwar: Our testing is CarlFK :-P | 04:39 |
| CarlFK | I have a test! | 04:40 |
| CarlFK | I wrote 3 maybe. not sure 2 of them really work. but I got Jenkins to run one. once. | 04:40 |
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| benreynwar | mithro: Gonna watch your video now. Cheers for the link. | 04:53 |
| CarlFK | mithro: https://travis-ci.org/timvideos/HDMI2USB-litex-firmware/jobs/423491996#L2800 Platform: opsis Target: hdmi2usb (default: video) | 05:14 |
| CarlFK | it built - does it get pushed to https://github.com/timvideos/HDMI2USB-firmware-prebuilt right away, or wait for all the flavors to build ? | 05:14 |
| tpb | Title: GitHub - timvideos/HDMI2USB-firmware-prebuilt: Prebuilt firmware for the HDMI2USB devices (such as the Numato Opsis and the Digilent Atlys board) and OS drivers. (at github.com) | 05:14 |
| CarlFK | mithro: never mind - I found v0.0.4-277-g2b3ff04 2 hours ago - I'll try that | 05:17 |
| CarlFK | mithro: if I have the right udev rules, should this need sudo? sudo hdmi2usb-mode-switch -v --mode serial | 05:23 |
| mithro | CarlFK: no, it should not | 05:34 |
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| mithro | CarlFK: assuming your in the right groups.... | 05:35 |
| CarlFK | mithro: good news - test pattern: https://veyepar.nextdayvideo.com/static/temp/v0.0.4-277-g2b3ff04.png | 05:35 |
| CarlFK | mithro: what group do I need? im in: juser dialout sudo audio video plugdev | 05:37 |
| CarlFK | 05:37 | |
| mithro | CarlFK: they look right... | 05:39 |
| CarlFK | mithro: k - I'll try again in a bit without sudo and see what happens | 05:40 |
| cr1901_modern | xobs: Just checked. This is a yosys error I think | 05:51 |
| cr1901_modern | err s/error/bug/ | 05:52 |
| cr1901_modern | It should accept "-" in filenames | 05:52 |
| xobs | <freenode_cr1 "xobs: Just checked. This is a yo"> cr1901_modern: is that a valid verilog module name, though? It's not like C, where module names are [a-zA-Z0-9]? | 05:53 |
| cr1901_modern | Oh... right | 05:53 |
| cr1901_modern | err... dunno :P | 05:53 |
| xobs | If you keep the filename the same but just change the module name, it works. | 05:54 |
| cr1901_modern | yes looks like you're correct, whoops | 05:54 |
| CarlFK | mithro: more good news: https://veyepar.nextdayvideo.com/static/temp/v0.0.4-277-g2b3ff04.pi.png | 05:58 |
| cr1901_modern | xobs: Yea, my change royally broke LiteX too, I'm fixing it now | 05:58 |
| CarlFK | mithro: ^^ test rig is working again. helps to plug the pi's hdmi into the Opsis :p | 05:58 |
| CarlFK | mithro: more goodness: on the pi: pi@oppi:~ $ sudo fbi --vt 1 1280x720_input.png - captured: https://veyepar.nextdayvideo.com/static/temp/v0.0.4-277-g2b3ff04.pi.test.png | 06:09 |
| cr1901_modern | xobs: See gitter. I don't think I'm solving this tonight unless Dolu1990 gets back to me real fast | 06:12 |
| xobs | No hurry. It's easy enough to rename it. | 06:13 |
| mithro | Hrm, apparently you can't have a C++ compiler without a C std library... | 06:15 |
| mithro | hey xobs | 06:26 |
| mithro | how are things in Singapore? | 06:26 |
| CarlFK | mithro: somewhere are some test pattern images. or code to generate them. any idea where? | 06:32 |
| mithro | CarlFK: https://github.com/timvideos/test-patterns | 06:35 |
| tpb | Title: GitHub - timvideos/test-patterns: Test patterns for debugging video problems. (at github.com) | 06:35 |
| mithro | That was my first guess | 06:35 |
| CarlFK | good guess :p | 06:35 |
| mithro | CarlFK: I feel like I need a "swear jar" type thing where you put coin into everytime you ask me about something you should have guess.... | 06:37 |
| cr1901_modern | "I'm not gonna swear, but I am going to KICK THIS DOGHOUSE DOWN!!" | 06:38 |
| CarlFK | lol | 06:38 |
| xobs | mithro: Singapore is warm like usual. I'm starting over on the coriolis stuff. I found out its not dead, just that work continued on a branch I didn't know about... | 06:40 |
| mithro | xobs: Damn | 06:40 |
| xobs | It's not a total loss - at least it's not dead! And now I know more about its internals than I otherwise would have. | 06:40 |
| mithro | xobs: Finally booked my OrConf trip | 06:45 |
| xobs | Oh excellent. When do you get there? | 06:45 |
| mithro | 2pm the 20th | 06:46 |
| xobs | Neat. I get there at 8am the day before. | 06:47 |
| mithro | cr1901_modern: https://docs.google.com/document/d/1kjqIXAhxrKkS9QNSgT0npHPRNLpzaJuKji5_jVxN-Nk/edit#heading=h.43f9feq9mwoc | 06:57 |
| tpb | Title: FuPy - Adding new board HowTo - Google Docs (at docs.google.com) | 06:57 |
| cr1901_modern | Last edit August 13, 2017. Has it really been that long already ._.? | 06:59 |
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| mithro | tinyfpga: how did you go in the end? | 07:24 |
| tinyfpga | mithro: i have custom RAM blocks working, I got the SPI core working with correct data, and I implemented a simple pulse density modulation core for use as a DAC and/or LED control | 07:29 |
| tinyfpga | mithro: learned a lot about litex/migen | 07:29 |
| tinyfpga | mithro: I think my next step is pulling in USB components | 07:30 |
| tinyfpga | mithro: and adapting them for litex...I have some ideas now that I know how it works | 07:30 |
| mithro | tinyfpga: would be good to upload your tests so we can see how your going | 07:31 |
| tinyfpga | mithro: I’m still using the UART wishbone bridge, I was having trouble getting arachnepnr to successfully route the soc with lm32 enabled | 07:32 |
| mithro | tinyfpga: there are a bunch of patterns / antipatterns that you pick up from _florent_ | 07:32 |
| mithro | tinyfpga: cr1901_modern has some suggestions for a better "minimal" lm32 config | 07:32 |
| tinyfpga | mithro: yeah, I just followed the TinyFPGA SoC example...so I’m sure there are things that can be changed | 07:33 |
| tinyfpga | mithro: once i have my USB core working and a CPU core is ready, I’ll be moving to an embedded CPU core for most work | 07:33 |
| mithro | tinyfpga: _florent_ threw that together at CCC if I recall correctly | 07:33 |
| mithro | Still very much a WIP | 07:34 |
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| _florent_ | mithro: yes the idea was just to have a first version working. The minimal config is for another usage (code in rom), we could think about the best variants to create and i'm open to changing that | 08:58 |
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| shorne | CarlFK: mithro: I am basically the maintainer for qemu, I am happy to support the litex configuration. I know we will be using it. Let me know when you are ready for upstreaming and I can review before we send the patches upstream. | 11:54 |
| shorne | I am a bit busy for the next two weeks though. I am between jobs and have to study for some kind of certification test before I start the next job. | 11:55 |
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| tinyfpga | _florent_: this is my first time using litex/migen and I am _really_ liking it | 15:50 |
| CarlFK | tumbleweed: The repository 'http://ppa.launchpad.net/timvideos/fpga-support/ubuntu cosmic Release' does not have a Release file. | 16:11 |
| tpb | Title: Index of /timvideos/fpga-support/ubuntu (at ppa.launchpad.net) | 16:11 |
| tumbleweed | CarlFK: copied to cosmic. Wait for the publisher to come round | 16:34 |
| CarlFK | tumbleweed: thanks again - hope you can tollerate the slow dribble of discovery | 16:34 |
| CarlFK | tumbleweed: shorne: i'm curious - any idea why "apt build-dep qemu" ends with update-initramfs: Generating /boot/initrd.img-4.17.0-9-generic | 16:35 |
| tumbleweed | CarlFK: because of an indirect dependency on e2fsprogs and xfsprogs | 16:46 |
| CarlFK | ok, I can kinda accept that. | 16:47 |
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| _florent_ | tinyfpga: great :) | 17:12 |
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| CarlFK | shorne: do you remember this from about 8 moths ago I think: util/memfd.c:40:12: error: static declaration of ‘memfd_create’ http://paste.ubuntu.com/p/ZVM366Ckgm/ | 17:18 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 17:18 |
| CarlFK | I found some accepted patches, manually fixed up the 4 or 5 in https://github.com/timvideos/qemu-litex but ran into another fail that was similar: I found talk about it, but couldn't find patches. | 17:20 |
| tpb | Title: GitHub - timvideos/qemu-litex (at github.com) | 17:20 |
| CarlFK | I'm trying to figure out how to get it to build so we can consider upstreaming | 17:22 |
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| CarlFK | mithro: should/can I re-run just this one: https://travis-ci.org/timvideos/HDMI2USB-litex-firmware/jobs/423504612#L4345 The job exceeded the maximum time limit for jobs, and has been terminated. | 19:42 |
| mithro | _florent_: did you see I started collecting a lot of the LiteX related docs here -> https://github.com/timvideos/litex-buildenv/wiki | 20:26 |
| tpb | Title: Home · timvideos/litex-buildenv Wiki · GitHub (at github.com) | 20:26 |
| mithro | tinyfpga: would love to get feedback, it's always interesting to see new people who have had other experiences try LiteX | 20:27 |
| tinyfpga | mithro: yeah, I will be providing feedback and massaging the soc example for florent | 21:00 |
| tinyfpga | mithro: I want to make it easy for people to use and understand so they can extend it | 21:01 |
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| tinyfpga | xobs, cr1901_modern, mithro: what’s needed for vexriscv to work well in litex? | 22:19 |
| tinyfpga | once I have my USB IP implemented and working for litex I want to get it running with a soft core | 22:19 |
| CarlFK | tinyfpga: do you know about the usb problems with htmi2usb? | 22:51 |
| tinyfpga | CarlFK: nope, not familiar with those problems | 22:52 |
| CarlFK | 1 - send chars too fast, most get lost (queue overflow?) | 22:52 |
| CarlFK | 2 - connect to the serial interface first (/dev/ttyACM0) that somehow screws up /dev/video0 | 22:53 |
| tinyfpga | CarlFK: I’m working with the USB IP from the TinyFPGA Bootloader | 22:53 |
| CarlFK | but connect to /dev/video0 first and all is well | 22:53 |
| CarlFK | well... if you are becomeing a usb expert.. please looookkkkk!!!! | 22:53 |
| tinyfpga | CarlFK: both the video device and serial device are over usb? | 22:53 |
| CarlFK | I'm only an expert at whining about it :p | 22:54 |
| CarlFK | yes | 22:54 |
| CarlFK | video is like a usb webcam | 22:54 |
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| CarlFK | mithro: can I close issues I opened? like https://github.com/timvideos/HDMI2USB-litex-firmware/issues/431 | 23:30 |
| tpb | Title: usb stream broken · Issue #431 · timvideos/HDMI2USB-litex-firmware · GitHub (at github.com) | 23:30 |
| CarlFK | seems to be fixed. | 23:30 |
| CarlFK | tinyfpga: https://github.com/timvideos/HDMI2USB-fx2-firmware/issues/14 | 23:34 |
| tpb | Title: Having the serial port open prevents video from streaming · Issue #14 · timvideos/HDMI2USB-fx2-firmware · GitHub (at github.com) | 23:34 |
| CarlFK | mithro: another I think can be closed - this one you opened: https://github.com/timvideos/HDMI2USB-litex-firmware/issues/80 | 23:35 |
| tpb | Title: Support resetting an video input without resetting the output · Issue #80 · timvideos/HDMI2USB-litex-firmware · GitHub (at github.com) | 23:35 |
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