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| CarlFK | mithro: https://github.com/timvideos/qemu-litex.git doesn't build on 18.04 lts | 00:05 |
|---|---|---|
| tpb | Title: GitHub - timvideos/qemu-litex (at github.com) | 00:05 |
| mithro | Yes I think it needs to be rebased | 00:05 |
| CarlFK | can the changes you/someone made be upstreamed? | 00:16 |
| CarlFK | mithro: ^^ hoping I can get a qemu hacker to work it all out. | 00:16 |
| mithro | CarlFK: That would take a lot of time | 00:19 |
| mithro | CarlFK: https://github.com/mithro/qemu/branches/all?utf8=%E2%9C%93&query=litex- | 00:20 |
| tpb | Title: Branches · mithro/qemu · GitHub (at github.com) | 00:20 |
| mithro | CarlFK: Have to chat with shorne to get a better idea of what of my stuff has already gone upstream - I don't think much | 00:21 |
| mithro | CarlFK: There might be some stuff here too -> https://github.com/mithro/qemu-litex/branches/all | 00:21 |
| tpb | Title: Branches · mithro/qemu-litex · GitHub (at github.com) | 00:21 |
| mithro | shorne: Do you know if these changes were merged upstream? https://github.com/mithro/qemu/branches/all?utf8=%E2%9C%93&query=or1k | 00:22 |
| tpb | Title: Branches · mithro/qemu · GitHub (at github.com) | 00:22 |
| mithro | CarlFK: No idea what the status of those branches is either | 00:23 |
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| * mithro is going to head home and continue doing the documentation update from there... | 01:00 | |
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| shorne | mithro: for qemu patches. I dont think the litex hardware description was. | 14:16 |
| shorne | the evbar changes were (to allow different memory maps) | 14:16 |
| shorne | I think the cpucfg one was | 14:17 |
| shorne | Please let me know if you want to get all that stuff upstream we can work on a plan. I know there are kernel patches too for the evbar support | 14:18 |
| CarlFK | shorne: re qemu - my guess is he would like all of it upstream, but do the qemu devs see enough value in it to maintain the additional code forever ? | 14:48 |
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| mithro | Hey shorne | 15:56 |
| mithro | cr1901_modern: Did you have any luck yesterday? | 15:56 |
| mithro | shorne: Any chance your still around? | 15:58 |
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| mithro | Hrm, is it HowTo or Howto ? | 16:22 |
| CarlFK | lol - "It is common practice to write the phrase as "HOWTO" in the open-source community" https://en.wikipedia.org/wiki/How-to | 16:24 |
| tpb | Title: How-to - Wikipedia (at en.wikipedia.org) | 16:24 |
| CarlFK | " As of 2009 A Google search for "How To" results in a comprehensive list of HowTo sites." | 16:26 |
| CarlFK | HowTo - given nowhere do I see Howto | 16:27 |
| cr1901_modern | mithro: No, and I took a break from it yesterday soon after b/c it was irritating me | 16:28 |
| mithro | CarlFK: I started moving the Google Doc for LCA2018 FPGA Miniconf to https://github.com/timvideos/litex-buildenv/wiki/HowTo-LCA2018-FPGA-Miniconf | 16:33 |
| tpb | Title: HowTo LCA2018 FPGA Miniconf · timvideos/litex-buildenv Wiki · GitHub (at github.com) | 16:33 |
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| mithro | xobs: Do you have thoughts on Zephyr verse ChibiOS? | 16:38 |
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| CarlFK | mithro: the irc link doesn't get me into #linux.conf.au | 16:44 |
| mithro | ? | 16:44 |
| mithro | CarlFK: You mean the webchat thingy? | 16:44 |
| CarlFK | mithro: and because of the freenode spam, cfk2 == Cannot send to channel: #timvideos | 16:45 |
| CarlFK | mithro: yes. | 16:45 |
| mithro | CarlFK: okay | 16:45 |
| mithro | CarlFK: The aim is to eventually split the FPGA Miniconf page out into sections | 16:46 |
| CarlFK | mithro: im guessing you can drop the #lca bit | 16:46 |
| mithro | Yeah, possibly | 16:46 |
| mithro | One of the things I did like about the Google Doc was how easy it was for people to suggest changes... | 16:48 |
| CarlFK | tumbleweed: if you are around, can you bump the PPA stuff for cosmic? | 16:48 |
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| mithro | CarlFK: I started splitting out the udev rules into their own repo -> https://github.com/timvideos/litex-buildenv-udev | 17:06 |
| tpb | Title: GitHub - timvideos/litex-buildenv-udev: udev rules for LiteX BuildEnv supported boards (at github.com) | 17:06 |
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| CarlFK | mithro: nice - i | 17:08 |
| mithro | CarlFK: I was ponder if we should split the HDMI2USB udev rules from the FPGA dev board rules or not... | 17:09 |
| CarlFK | mithro: nice - i'm still fuzzy on how to diagnose what is going on, like if some other udev rule is interfering | 17:09 |
| mithro | CarlFK: I don't trust your machine if you are still using the ppas... | 17:10 |
| CarlFK | mithro: keep hdmi2usb and dev stuff together. | 17:11 |
| CarlFK | "the ppas" is a little vague . I seem to remember a command, probably udevadm, that would show as rules fired.. know what I am talking about? or should I dig into my firewire history of years ago... | 17:16 |
| mithro | https://github.com/timvideos/litex-buildenv-udev#examining-udev-data maybe? | 17:17 |
| tpb | Title: GitHub - timvideos/litex-buildenv-udev: udev rules for LiteX BuildEnv supported boards (at github.com) | 17:17 |
| CarlFK | mithro: here we go (should have skimmed man first) udevadm monitor - Listens to the kernel uevents and events sent out by a udev rule and prints the devpath of the event to the console. | 17:18 |
| CarlFK | mithro: power cycling the opsis: http://paste.ubuntu.com/p/qGTmP8VPpD/ | 17:23 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 17:23 |
| mithro | CarlFK: That looks all good | 17:24 |
| CarlFK | mithro: yay. any idea what (media) is about? KERNEL[815216.554497] add /devices/pci0000:00/0000:00:1c.7/0000:07:00.0/usb3/3-1/3-1:1.0/media9 (media) | 17:24 |
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| mithro | Nope! | 17:27 |
| mithro | UDEV [815216.579193] add /devices/pci0000:00/0000:00:1c.7/0000:07:00.0/usb3/3-1/3-1:1.2/tty/ttyACM0 (tty) | 17:28 |
| mithro | UDEV [815216.581634] add /devices/pci0000:00/0000:00:1c.7/0000:07:00.0/usb3/3-1/3-1:1.0/video4linux/video0 (video4linux) | 17:28 |
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| mithro | lunch time for me! | 19:58 |
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| CarlFK | synaption[m]: are you expecting me at ps1 today? | 20:00 |
| CarlFK | mithro: I have one of these https://www.monoprice.com/product?p_id=30459 | 20:06 |
| tumbleweed | CarlFK: I am around now | 20:06 |
| CarlFK | plugged in a usb cable, dmesg/syslog/lsusb doesn't show anything. | 20:06 |
| CarlFK | tumbleweed: super low priority, but would be handy if the PPAs worked with cosmic | 20:07 |
| CarlFK | tumbleweed: like right now I am trying to see if a with a newer kernel solves something like this problem: https://lore.kernel.org/patchwork/patch/650104/ | 20:12 |
| tpb | Title: [net,v3] r8169:fix "rtl_counters_cond == 1 (loop: 1000, delay: 10)" log spam. - Patchwork (at lore.kernel.org) | 20:12 |
| CarlFK | because: juser@cnt6:~/bin$ dmesg |wc -> 2046 22506 186186 | 20:13 |
| CarlFK | juser@cnt6:~/bin$ dmesg |grep -v rtl_counters_cond |wc -> 0 0 0 | 20:13 |
| tumbleweed | CarlFK: which PPA? | 20:13 |
| CarlFK | it eats all my dmesg !! | 20:13 |
| CarlFK | um.. whatever ansible used :p | 20:14 |
| CarlFK | sec.. I think I can find the error | 20:14 |
| CarlFK | tumbleweed: 'http://ppa.launchpad.net/timvideos/voctomix/ubuntu cosmic Release' does not have a Release file.\n | 20:16 |
| tpb | Title: Index of /timvideos/voctomix/ubuntu (at ppa.launchpad.net) | 20:16 |
| tumbleweed | CarlFK: copied. It'll take half an hour to publish, probably | 20:24 |
| CarlFK | tumbleweed: thank you! | 20:24 |
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| CarlFK[m] | https://matrix.to/#/!RMqIGGkygXzUHQVswl:matrix.org/$1535833488335969weatD:matrix.org | 20:49 |
| CarlFK | hey... where is my image?! | 20:50 |
| * CarlFK[m] uploaded an image: 20180901_152356.jpg (800KB) < https://matrix.org/_matrix/media/v1/download/matrix.org/eyjxIboeTXACZRYcibnMoaUw > | 20:50 | |
| tinyfpga | mithro: how do I use the PLL in litex? | 20:52 |
| mithro | tinyfpga: Your PLL is just a primitive you instantiate directly, right? | 20:53 |
| tinyfpga | mithro: is there a standard way to do it fornice40+litex or should instantiate the PLL module myself? | 20:53 |
| tinyfpga | mithro: ok, so litex doesn’t do anything special for PLLs then | 20:53 |
| mithro | tinyfpga: Not at the moment | 20:54 |
| mithro | tinyfpga: See https://github.com/timvideos/litex-buildenv/blob/master/targets/arty/base.py#L21-L101 ? | 20:54 |
| tpb | Title: litex-buildenv/base.py at master · timvideos/litex-buildenv · GitHub (at github.com) | 20:54 |
| tinyfpga | mithro: next question, how do I use the UARTWishboneBridge? | 20:54 |
| tinyfpga | mithro: i enabled it in my soc, but now I want to talk to the soc from my host computer | 20:54 |
| mithro | tinyfpga: You'll probably want multiple clock domains | 20:54 |
| tinyfpga | mithro: yes, ultimately I will want multiple clock domains, but I’m trying to get up on my feet first | 20:55 |
| tinyfpga | mithro: I’m not at all familiar with litex/migen | 20:55 |
| mithro | tinyfpga: Basically you start the litex_server using something like "litex_server uart [port] [baudrate]" | 20:57 |
| mithro | tinyfpga: Then you can connected to it using a python console | 20:58 |
| mithro | tinyfpga: I use this script -> https://github.com/timvideos/litex-buildenv/blob/master/test/ipython_etherbone.py | 20:59 |
| tpb | Title: litex-buildenv/ipython_etherbone.py at master · timvideos/litex-buildenv · GitHub (at github.com) | 20:59 |
| mithro | tinyfpga: the litex-buildenv tests/ipython_etherbone.py will auto start the required proxy for uart/pcie | 21:02 |
| tinyfpga | Nice | 21:02 |
| mithro | https://github.com/timvideos/litex-buildenv/blob/master/test/common.py#L17-L31 | 21:02 |
| tpb | Title: litex-buildenv/common.py at master · timvideos/litex-buildenv · GitHub (at github.com) | 21:02 |
| mithro | tinyfpga: It's all based around etherbone.... | 21:04 |
| tinyfpga | mithro: ok, I’m working on getting litex on Windows so can access the serial port | 21:06 |
| * CarlFK[m] uploaded an image: 20180901_155924.jpg (758KB) < https://matrix.org/_matrix/media/v1/download/matrix.org/eyQljgByuekGAdMgIGklcDoE > | 21:06 | |
| mithro | tinyfpga: _florent_ and cr1901_modern use Windows a bit | 21:07 |
| * CarlFK[m] uploaded an image: 20180901_160329.jpg (769KB) < https://matrix.org/_matrix/media/v1/download/matrix.org/yQZBcGKpGNbgwVQewkYMtVzF > | 21:09 | |
| mithro | CarlFK: O | 21:10 |
| mithro | CarlFK: I'm pretty sure we wouldn't be able to get those parts | 21:10 |
| CarlFK | mithro: really hoping to be able to just buy the unit and flash new custom firmware | 21:11 |
| CarlFK | last chip coming up... | 21:11 |
| mithro | CarlFK: I highly doubt it | 21:12 |
| * CarlFK[m] uploaded an image: 20180901_160517.jpg (786KB) < https://matrix.org/_matrix/media/v1/download/matrix.org/coShGAfGsJdgwgoVAzFJpBhM > | 21:12 | |
| CarlFK | rats. It is a nice size for a test pattern generator | 21:12 |
| mithro | CarlFK: https://www.latticesemi.com/-/media/LatticeSemi/Documents/DataSheets/ASSP/SiI-DS-1120_Public.ashx?document_id=51629 | 21:13 |
| mithro | http://www.latticesemi.com/Products/ASSPs/HomeTheaterVideoProcessors | 21:13 |
| tpb | Title: Home Theater Video Processors - Lattice Semiconductor (at www.latticesemi.com) | 21:13 |
| CarlFK | mithro: it has a "USB port for performing a system software update." | 21:14 |
| mithro | CarlFK: Nothing you posted so far as firmware in it... | 21:16 |
| mithro | CarlFK: Just image encoder / decoder... | 21:16 |
| CarlFK | mithro: there's a heat sink over a chip. guessing thats an fpga | 21:17 |
| tinyfpga | mithro: what’s the “common” package in the ipython_etherbone.py script? | 21:17 |
| CarlFK | my guess is kinda based on "well everything these days is an fpga, and what else could be updated over usb?" | 21:17 |
| mithro | CarlFK: It's like just a management SoC | 21:18 |
| mithro | CarlFK: Probably something like http://www.latticesemi.com/Products/ASSPs/HomeTheaterVideoProcessors | 21:19 |
| tpb | Title: Home Theater Video Processors - Lattice Semiconductor (at www.latticesemi.com) | 21:19 |
| tinyfpga | mithro: nm, I found the rest of the project :) | 21:19 |
| mithro | Hrm... | 21:20 |
| mithro | tinyfpga: the common.py are just some quick tools for getting some useful probing tools | 21:21 |
| CarlFK | mithro: well, the good news is I can power it with a usb battery and it will spit out a 720p black with a green "no signal" box that floats around. so ... kinda lets me see if a projector is working. | 21:25 |
| tinyfpga | mithro: ok, so now it’s complaining about csr.csv....I’m assuming that’s the config register map? I don’t see this being generated as part of the litex build of TinyFPGA SoC | 21:26 |
| mithro | tinyfpga: Yeah | 21:26 |
| mithro | tinyfpga: https://github.com/timvideos/litex-buildenv/blob/master/make.py#L138-L139 | 21:27 |
| tpb | Title: litex-buildenv/make.py at master · timvideos/litex-buildenv · GitHub (at github.com) | 21:27 |
| mithro | Opps | 21:27 |
| mithro | tinyfpga: https://github.com/timvideos/litex-buildenv/blob/master/make.py#L119-L121 | 21:28 |
| tpb | Title: litex-buildenv/make.py at master · timvideos/litex-buildenv · GitHub (at github.com) | 21:28 |
| tinyfpga | mithro: ok, thanks | 21:28 |
| tinyfpga | :) | 21:28 |
| mithro | tinyfpga: Things are still a bit of a mess - I'm hoping that we can clean some of it up with the lxbe-tool stuff | 21:30 |
| mithro | tinyfpga: going to get coffee be back later.. | 21:37 |
| mithro | tinyfpga: you might be better of doing most of your dev on the arty and then switching afterwards - having tftp boot firmware and wishbone over Ethernet is really nice | 21:44 |
| tinyfpga | mithro: I already have the UART wishbone bridge connected and a programmer connected to the board | 21:46 |
| tinyfpga | mithro: this will help me learn migen/litex better | 21:46 |
| tinyfpga | mithro: by the way, how do I instantiate a Verilog module from migen/litex? Looking for examples I don’t see much | 21:47 |
| mithro | It's all about the csrs | 21:47 |
| mithro | Unless it's timing critical, move it into firmware | 21:47 |
| tinyfpga | mithro: agreed, but I need to instantiate the PLL | 21:48 |
| tinyfpga | mithro: then I will instantiate the front-end of the USB hardware | 21:49 |
| mithro | cr1901_modern: probably has an ice40 example of PLL in Migen somewhere... | 21:49 |
| tinyfpga | mithro: I’m pretty happy to move as much as possible to software | 21:49 |
| mithro | Yeah, C is so much easier to write :-) | 21:50 |
| tinyfpga | mithro: I just need an example or documentation of any Verilog module being instantiate in migen/litex | 21:50 |
| tinyfpga | mithro: maybe florents USB3 test does that... | 21:50 |
| mithro | https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers#specials | 21:51 |
| tpb | Title: LiteX for Hardware Engineers · timvideos/litex-buildenv Wiki · GitHub (at github.com) | 21:51 |
| tinyfpga | mithro: thanks!! | 21:53 |
| cr1901_modern | tinyfpga: http://ix.io/1lM9 | 21:55 |
| tinyfpga | cr1901_modern: awesome! :) I’ll be using this.... | 21:55 |
| cr1901_modern | tinyfpga: I did this elsewhere in the project I yanked this from, but you'll also want: "m.clock_domains.cd_sys = ClockDomain()" | 21:56 |
| tinyfpga | mithro, cr1901_modern: ok, I can now read and write the FPGA blockram from my computer XD | 22:17 |
| mithro | tinyfpga: \o/ | 22:17 |
| mithro | tinyfpga: Good first step | 22:17 |
| tinyfpga | mithro: it’s starting to make more sense | 22:18 |
| tinyfpga | mithro: being able to access the soc from my computer is fantastic | 22:18 |
| mithro | tinyfpga: It is :-P | 22:18 |
| mithro | tinyfpga: The problem is you quickly get use to it.... | 22:18 |
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| mithro | cr1901_modern: Thoughts on https://github.com/timvideos/litex-buildenv/wiki/Targets ? | 22:38 |
| tpb | Title: Targets · timvideos/litex-buildenv Wiki · GitHub (at github.com) | 22:38 |
| cr1901_modern | Perhaps base should be split into "base" (as described) and "base-lite" (using SPIflash for ROM, internal blockram for SDRAM)? | 22:43 |
| mithro | cr1901_modern: Hrm - that is almost min with the addition of spiflash? | 22:44 |
| cr1901_modern | I actually see it more as "base with the detriment of spiflash", b/c spiflash execution is still usable for things you'd expect from a base system like micropython | 22:45 |
| cr1901_modern | for instance, tinyfpga will make a good upy system, but only if it can execute from spiflash. But it'll never get targets more complex than that (no offense tinyfpga :P) | 22:46 |
| mithro | cr1901_modern: Is there any reason you /wouldn't/ want external ram? | 22:47 |
| tinyfpga | cr1901_modern: hey, maybe the _BX_ won’t get much more complex XD | 22:47 |
| cr1901_modern | mithro: If the board doesn't come with one... | 22:47 |
| mithro | cr1901_modern: Then it's not in base.py | 22:47 |
| tinyfpga | cr1901_modern: you can have external SPI SRAM | 22:48 |
| cr1901_modern | ahhh, nevermind then | 22:48 |
| * mithro changes the wording to "on board memory interfaces" | 22:48 | |
| mithro | I guess you could have a hyperram pmod... | 22:48 |
| cr1901_modern | Sure, but let's cross that bridge later. you clarified my confusion | 22:49 |
| mithro | cr1901_modern: But that shouldn't be part of the "base" config | 22:49 |
| cr1901_modern | That's fine then | 22:49 |
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| mithro | https://github.com/timvideos/litex-buildenv/wiki/Environment-Options | 22:58 |
| tpb | Title: Environment Options · timvideos/litex-buildenv Wiki · GitHub (at github.com) | 22:59 |
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| tinyfpga | cr1901_modern: do you know how to implement a custom Memory to be added to the wishbone interconnect in litex? | 23:28 |
| tinyfpga | cr1901_modern: or do you know of any examples? | 23:28 |
| tinyfpga | cr1901_modern: maybe the best option is to just implement it as a wb slave | 23:30 |
| mithro | tinyfpga: BTW If you don't say my name I won't necessarily see your request :-) | 23:33 |
| mithro | tinyfpga: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc_core.py#L163 | 23:33 |
| tpb | Title: litex/soc_core.py at master · enjoy-digital/litex · GitHub (at github.com) | 23:33 |
| mithro | tinyfpga: These are probably the lines you want -> https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc_core.py#L162-L168 | 23:34 |
| tpb | Title: litex/soc_core.py at master · enjoy-digital/litex · GitHub (at github.com) | 23:34 |
| CarlFK | mithro: is there a text file of | 23:40 |
| CarlFK | er... | 23:40 |
| CarlFK | mithro: is there a text file of firmware build results? so I can find other opsis-hdmi2usb to try | 23:41 |
| tinyfpga | mithro: yeah, I found I need to make my own version of SRAM | 23:42 |
| mithro | CarlFK: what do you mean? | 23:42 |
| mithro | tinyfpga: What do you mean? | 23:42 |
| mithro | tinyfpga: You should be able to just import that wishbone.SRAM module and add another? | 23:43 |
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| CarlFK | mithro: I want to try other firmware builds, but I am not sure how to find successful builds - I can use download-prebuilt-firmware.py but I may hit the github limit | 23:44 |
| mithro | benreynwar: We have been hacking on litex-buildenv here most of the day | 23:44 |
| mithro | benreynwar: tinyfpga has been learning migen | 23:44 |
| mithro | CarlFK: Did we move to github pages based stuff? | 23:45 |
| mithro | s/Did/Didn't/ | 23:45 |
| benreynwar | mithro: Cool. I saw that you were involved in litex. | 23:45 |
| mithro | CarlFK: https://github.com/timvideos/HDMI2USB-firmware-prebuilt/tree/gh-pages | 23:45 |
| tpb | Title: GitHub - timvideos/HDMI2USB-firmware-prebuilt at gh-pages (at github.com) | 23:45 |
| CarlFK | mithro: I remember talking about it. that's all I remember. | 23:46 |
| mithro | benreynwar: I'm probably the biggest FOSS user outside of _florent_ | 23:46 |
| mithro | CarlFK: I forget where then end up getting published | 23:46 |
| benreynwar | mithro: I looked at migen a couple of years ago, but decided I needed to be conservative and stick to VHDL. I'm kind of regretting it now! | 23:46 |
| mithro | benreynwar: What are you doing again? | 23:46 |
| mithro | benreynwar: I made the same decision along while back - have you seen my talk about it? | 23:47 |
| mithro | CarlFK: They end up here -> https://code.timvideos.us/HDMI2USB-firmware-prebuilt/ | 23:47 |
| benreynwar | mithro: At work I do LPDC error correction cores. | 23:48 |
| mithro | LPDC? | 23:48 |
| benreynwar | mithro: Haven't seen your talk. Where's it at? | 23:48 |
| benreynwar | Low density parity check. It's an error correction algorithm. | 23:48 |
| CarlFK | mithro: is there a list of all the builds? | 23:48 |
| mithro | benreynwar: BTW You should look at cocotb it your intested in better verilog testing... | 23:48 |
| mithro | benreynwar: https://www.youtube.com/watch?v=181-roBM0tI | 23:48 |
| benreynwar | mithro: Got to take the kids to the park now, but will likely be back on this evening. | 23:49 |
| mithro | CarlFK: https://code.timvideos.us/HDMI2USB-firmware-prebuilt/revs.txt | 23:49 |
| mithro | CarlFK: even sorted for you in the right way... | 23:49 |
| mithro | CarlFK: https://code.timvideos.us/HDMI2USB-firmware-prebuilt/index.txt | 23:50 |
| mithro | CarlFK: You probably won't hit github limits with those URLs.. | 23:51 |
| CarlFK | mithro: revs.txt is the only one that looks like it might have what I want, any idea what it represents? | 23:52 |
| mithro | CarlFK: it's a listing of the directories under archive | 23:53 |
| mithro | https://github.com/timvideos/HDMI2USB-firmware-prebuilt/tree/gh-pages/opsis/hdmi2usb/lm32 | 23:53 |
| tpb | Title: HDMI2USB-firmware-prebuilt/opsis/hdmi2usb/lm32 at gh-pages · timvideos/HDMI2USB-firmware-prebuilt · GitHub (at github.com) | 23:53 |
| CarlFK | mithro: like I want opsis-htmi2usb.. hmm. so I still have to dig into each dir and see if there is an image file | 23:54 |
| mithro | CarlFK: Yes, but much quicker to do it | 23:56 |
| mithro | CarlFK: We could generate a full index if you want I guess... | 23:56 |
| mithro | CarlFK: https://github.com/timvideos/HDMI2USB-litex-firmware/blob/master/.travis/generate-prebuilt-list.py | 23:57 |
| tpb | Title: HDMI2USB-litex-firmware/generate-prebuilt-list.py at master · timvideos/HDMI2USB-litex-firmware · GitHub (at github.com) | 23:57 |
| mithro | benreynwar: I'll probably still be here | 23:58 |
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