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| xobs | Okay, getting started now on the actual HDL stuff. I need timing that's faster than 83ns, so I think I'll need to use a PLL. Is there documentation on how to do that? I see a Reddit post with some Verilog code from two years ago. | 06:56 |
|---|---|---|
| daveshah | xobs: have a look at the icepll tool included with icestorm | 07:00 |
| daveshah | That will create a Verilog module for you | 07:00 |
| daveshah | Just give it input and output frequency | 07:00 |
| xobs | daveshah: Oh neat. That looks like exactly what I want. How to I link to external verilog modules in migen? | 07:10 |
| daveshah | xobs: afraid I don't use migen much, so not sure | 07:11 |
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| cr1901_modern | xobs: Still awake? | 10:53 |
| cr1901_modern | xobs: Here's an example of how to use the PLL: https://gitlab.com/cr1901/fpga765/blob/master/fpga765/platform.py#L49-65 | 10:55 |
| tpb | Title: fpga765/platform.py · master · William D. Jones / fpga765 · GitLab (at gitlab.com) | 10:55 |
| cr1901_modern | You also need this line: https://gitlab.com/cr1901/fpga765/blob/master/fpga765/platform.py#L94 | 10:55 |
| tpb | Title: fpga765/platform.py · master · William D. Jones / fpga765 · GitLab (at gitlab.com) | 10:55 |
| daveshah | cr1901_modern: I don't think you need the SB_GB if you use PLLOUTGLOBAL, unless you're working around some kind of bug (don't know of any though) | 10:56 |
| cr1901_modern | I don't remember the rules, tbh. And I wrote this code over a year ago | 10:58 |
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| xobs | cr1901_modern: That's about what I got after talking with bunnie, but without the GBUF. I haven't synthesized it yet, however. | 11:11 |
| cr1901_modern | I don't remember why I put the GBUF there, I prob read it as part of the PLL user guide. | 11:16 |
| cr1901_modern | But it may very well not be required. I don't actually understand the icestorm docs- they are quite terse. | 11:17 |
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| cr1901_modern | _florent_: When you get the chance, could you upload your repo of your known-to-work lm32-on-tinyfpga? | 13:02 |
| cr1901_modern | I'd like to compare it to mine; last I checked, there was _definitely_ a synthesis mismatch in my repo | 13:03 |
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| daveshah | yeah, I'd quite like to see that too | 13:04 |
| _florent_ | cr1901_modern: i think i just commented these lines: | 13:04 |
| _florent_ | https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/lm32/verilog/lm32_config.v#L85 | 13:04 |
| tpb | Title: litex/lm32_config.v at master · enjoy-digital/litex · GitHub (at github.com) | 13:04 |
| _florent_ | and | 13:04 |
| _florent_ | https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/lm32/verilog/lm32_config.v#L93 | 13:04 |
| tpb | Title: litex/lm32_config.v at master · enjoy-digital/litex · GitHub (at github.com) | 13:04 |
| cr1901_modern | _florent_: Yes, but I thought you had a minimum example. I'll go ahead and try your config though | 13:04 |
| _florent_ | cr1901_modern: yes this one: https://github.com/enjoy-digital/tinyfpga-soc/blob/master/tinyfpga.py + the comments on lm32_config.v should work | 13:06 |
| tpb | Title: tinyfpga-soc/tinyfpga.py at master · enjoy-digital/tinyfpga-soc · GitHub (at github.com) | 13:06 |
| cr1901_modern | _florent_: tyvm | 13:06 |
| _florent_ | cr1901_modern: i think i was not running the standard bios but just custom firmware | 13:08 |
| cr1901_modern | That's perfectly fine right now | 13:08 |
| _florent_ | cr1901_modern: because bios was using too much memory | 13:08 |
| cr1901_modern | Right; the next thing I want to do is put your firmware onto flash and see what happens | 13:09 |
| cr1901_modern | But first I want to confirm things work on my end of course :) | 13:09 |
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| cr1901_modern | _florent_: Did you have to do anything special to make your SoC skip building the bios? | 13:23 |
| cr1901_modern | b/c it tries to build the bios anyway when I do "python3 tinyfpga.py", which naturally fails b/c no room | 13:23 |
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| cr1901_modern | Okay this is weird... the repo falls back to building the bios if firmware.bin can't be found | 13:25 |
| _florent_ | cr1901_modern: ah yes, possible | 13:26 |
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| cr1901_modern | Must be a litex-ism. I'll check in a bit but my guess is that if integrated_rom_init is empty list, litex tries building the bios | 13:26 |
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| cr1901_modern | fatal error: failed to place: placed 32 RAMs of 51 / 32 | 13:28 |
| cr1901_modern | _florent_: ^^ Can you check to see if you get this? | 13:31 |
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| cr1901_modern | Yea I definitely don't see how this firmware fits... | 13:40 |
| cr1901_modern | oh right, forgot to disable cache | 13:42 |
| _florent_ | cr1901_modern: ok i look at that | 13:42 |
| cr1901_modern | _florent_: I think I found the issue... I forgot to change lm32_config.v | 13:43 |
| _florent_ | cr1901_modern: yes, with that it's fine here | 13:50 |
| cr1901_modern | I'm _really_ surprised the design fits w/ a pipelined multiplier and barrel shifter | 13:52 |
| cr1901_modern | I deliberately disabled those, but I suspect that might be the source of my issues | 13:52 |
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| cr1901_modern | _florent_: I've attached your design + tinyfpga B to a logic analyzer. The LEDs work, but I've got nothing on the UART | 14:03 |
| cr1901_modern | Does this match behavior you've seen before? | 14:04 |
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| _florent_ | are you using the right pins for the uart? | 14:06 |
| _florent_ | also, have you compiled the firmware? | 14:07 |
| cr1901_modern | as far as I can tell, and firmware is compiled | 14:07 |
| cr1901_modern | Can't be rst signal b/c leds wouldn't be toggling if it was | 14:13 |
| cr1901_modern | _florent_: Could you please test on your end and see if the UART works when you get the chance? | 14:14 |
| cr1901_modern | and if it does, send me the build directory | 14:14 |
| cr1901_modern | I must be configuring something wrong | 14:14 |
| _florent_ | cr1901_modern: i'm not able to test now, maybe tomorrow | 14:16 |
| cr1901_modern | ack | 14:17 |
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