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| daveAgain | Hey was just going to ask about programmers for fpga chips support and an IDE for this project ????RECOMENDATIONS?? | 05:49 |
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| -_whitenotifier-3- [fpga-interchange-tests] kgugala opened issue #6: Add DCO check - https://git.io/JOiSO | 08:59 | |
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| -_whitenotifier-3- [fpga-interchange-schema] gatecat opened issue #41: Macro parameter mapping - https://git.io/JOPtS | 11:46 | |
| -_whitenotifier-3- [nextpnr] gatecat opened issue #284: FPGA Interchange Global Clock Routing - https://git.io/JOPmu | 11:58 | |
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| umarcor|2 | daveAgain: see https://terostechnology.github.io/terosHDLdoc/ | 13:55 |
| tpb | Title: Welcome to TerosHDL’s documentation! TerosHDL 0.1.4 documentation (at terostechnology.github.io) | 13:55 |
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| mithro | @gatecat I'm unsure the direction that litghost was planning to go regarding parameter mapping for things like LUTs / memory initialization details.... I'm pretty sure we discussed it at some point but can not remember the outcome... | 14:09 |
| gatecat | This is slightly separate from the LUTs issue | 14:09 |
| gatecat | that side of things is pretty well sorted now, it's specifically around splitting parameters for macros | 14:09 |
| mithro | gatecat: You could very well be right, I've been off doing other things so still trying to page a lot of stuff back into memory here.... | 14:12 |
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| gatecat | mithro: https://github.com/SymbiFlow/fpga-interchange-schema/issues/41#issuecomment-824880077 are my two suggested solutions to this, I'd be happy either way | 14:15 |
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