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| sf-slack | <prahitha.movva03> Hello mentors! I am Prahitha, an Outreachy applicant. I would like to contribute to the `Extend SystemVerilog test suite with functionality to filter the results` project. I was thinking of taking up issue #612. Looking forward to learning and contributing! :) | 10:25 |
|---|---|---|
| sf-slack | <kgugala> Hi @prahitha.movva03 | 10:27 |
| sf-slack | <kgugala> you may want to ping @tgorochowik about the issue | 10:27 |
| sf-slack | <kgugala> (@tgorochowik acually created it :)) | 10:27 |
| sf-slack | <tgorochowik> Sure, feel free to work on #612, please browse the `tests` dir to see the general structure of the tests, don't hesitate to ask if you have any questions | 10:32 |
| sf-slack | <prahitha.movva03> Thank you! | 10:33 |
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| -_whitenotifier-5- [fpga-interchange-schema] gatecat opened issue #24: Indexed strings in primLibs - https://git.io/JYw3S | 11:00 | |
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| sf-slack | <riddhima23singh> Thanks @mithro and @tbp, I was able to install it but how to build example design? Is there any simulator? | 11:46 |
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| litghost | Same link as above? Under "Building example designs"? | 16:25 |
| -_whitenotifier-5- [python-fpga-interchange] gatecat opened issue #47: Indexed strings in primLibs - https://git.io/JYrMY | 16:29 | |
| sf-slack | <riddhima23singh> @litghost Oh yes I was able to build them but I am not sure where to locate the bitstream and visualise it | 16:49 |
| litghost | I don't think your question is well formed? What are you trying to d? | 16:51 |
| sf-slack | <riddhima23singh> I built the examples, bitsream was generated as on the website led is flickering on the board how do I visualise it or observe without the board | 16:54 |
| sf-slack | <kgugala> you may want to run fasm2bels. This will give you structural verilog, which you can simulate | 16:55 |
| sf-slack | <riddhima23singh> okay thanks! That cleared my doubt. | 16:56 |
| sf-slack | <kgugala> this is the tool you may want to use https://github.com/SymbiFlow/symbiflow-xc-fasm2bels | 16:58 |
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| sf-slack | <prahitha.movva03> So I tried cloning the repo and running `git submodule update --init --recursive`, I get an error that opentitan, rsd, scr1 and tree-sitter-verilog failed to be cloned. Can I continue without those or should I try downloading them manually? Thanks! | 19:24 |
| litghost | which repo? | 19:26 |
| sf-slack | <prahitha.movva03> sv-tests | 19:26 |
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| sf-slack | <kgugala> what kind of error did you get | 20:03 |
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| sf-slack | <prahitha.movva03> I think it was a connection timed out error. It worked after running the same command a couple more times. Also, is it supposed to take this long to initialise all the submodules? | 21:34 |
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| FFY00_ | hey mithro, I was thinking of applying for the arch-defs wrapper generalization gsoc project. is there anyone else interested? is there anything in specific you want to point out? | 22:57 |
| FFY00_ | also, who would be mentoring it? | 22:57 |
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| mithro | litghost: How does https://github.com/SymbiFlow/prjxray-db/compare/master...mithro:master look? | 23:48 |
| litghost | I think the zynq segbit changes are bad | 23:49 |
| litghost | acomodi should look at the changes to the attrs.json | 23:50 |
| litghost | It looks suspecious, but I'm not sure | 23:50 |
| litghost | ports changes look good, same with the changes to the ppip files | 23:51 |
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