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| sf-slack4 | <arvindsrinivasan> This looks great as an improvement, thank you Lofty | 02:02 |
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| sf-slack4 | <dan.ravensloft> It's not a fix, but yeah | 02:03 |
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| sf-slack4 | <pingkan.wewengkang> Hi Everyone! I'm Cindy. I'm an FPGA engineer, and I'm interested to contribute to the open source FPGA projects. I am comfortable with Verilog and Python, and I have some experience with TCL scripting. Please do let me know of any available opportunities! | 21:52 |
| sf-slack4 | <dan.ravensloft> Welcome! | 22:57 |
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