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| hansfbaier | prjxray/build/tools/gen_part_base_yaml: not found <======= known issue when running fuzzers? | 00:27 |
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| sf-slack1 | <cheah.3> Hi guys, looking to start messing around with Symbiflow and RISC-V. I ordered one of those cheap 7010 boards from China, but I'd like to also try something out with the ICE40 or ECP5 since those chips seem to be better supported. Does anybody have a recommendation for cheap development boards? Tiny FPGA looks like it would fit the bill, but I can't find them in stock anywhere and it's not clear the developer is | 01:25 |
| sf-slack1 | supporting it anymore | 01:25 |
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| hansfbaier | sf-slack1: The Colorlight 5A-75B is unbeatable value. Not a dev board technically, but the value for money rocks | 01:32 |
| sf-slack1 | <cheah.3> any links to the docs on that one? which chip is on there? | 01:34 |
| hansfbaier | sf-slack1: https://github.com/q3k/chubby75 | 01:36 |
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| hansfbaier | sf-slack1: 25k LUTs | 01:37 |
| hansfbaier | sf-slack1: LEs rather | 01:38 |
| sf-slack1 | <cheah.3> Nice, seems pretty reasonable and amazon has them in stock. I was hoping for something with an actual schematic, but it looks like they've already documented the pinout pretty much | 01:50 |
| hansfbaier | sf-slack1: They are $14 now on AliExpress | 01:51 |
| sf-slack1 | <cheah.3> I might pick one up just for the hell of it then. Any other recommendations? I'd prefer something in the US so can work on it this week | 01:54 |
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| sf-slack1 | <rdz.fco89> I second this post. Pretty decent Verilog and Python knowledge. I am really interesed in helping this project move forward. | 02:14 |
| hansfbaier | sf-slack1: As for lattice boards, the colorlight seems to be as cheap as it can get. There are a lot of cool open hardware boards, but they are pricey, because manufactured in small quantities | 02:23 |
| hansfbaier | sf-slack1: If you want great value for money, the Litefury/Nitefury commercial variants named Acorn CLE-101 and CLE-215 for 100k or 200k LUTS each. You can get them second hand real cheap on ebay | 02:24 |
| hansfbaier | sf-slack1: Xilinx Artix-7 | 02:25 |
| hansfbaier | sf-slack1: You cant get an PCIe board that cheap anywhere else, usually will have to pay $500+ for PCIe boards | 02:25 |
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| umarcor | https://github.com/kelu124/awesome-latticeFPGAs | 03:07 |
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| sf-slack1 | <cheah.3> Thanks for the list, lots of good stuff in there. The colorlight i5 board looks interesting, i like the sodimm socket idea as you could build a new baseboard after development. https://a.aliexpress.com/_m0bwaot | 05:14 |
| tpb | Title: Gitter ECP5 FPGA RISC V Entwicklung Bord Farblicht i5 modul LFE5U Open Source Toolchain|Demo-Board| - AliExpress (at a.aliexpress.com) | 05:14 |
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| hansfbaier | 074-dump_all is running and running and already accumulated 57GB *gasp* .... my SSD is running full :( | 11:22 |
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| andrewb1999 | Is there a way to get an arbitrary litex design to map thro;ugh symbiflow? | 15:51 |
| andrewb1999 | I know there are issues with MMCMs but I'm not sure how to get litex to stop generating them | 15:52 |
| andrewb1999 | Are there any other issues I should know about as well? | 15:52 |
| sf-slack1 | <acomodi> @andrewb1999: I had done sth similar for a Litex-Linux design for the nexys-video. Basically, instead of the MMCM I instantiated a PLL by modifying the target python script | 15:57 |
| sf-slack1 | <acomodi> https://github.com/litex-hub/litex-boards/blob/9beaf25822c3794e14e8773778e014b3d7d9c80b/litex_boards/targets/nexys_video.py#L40 | 15:58 |
| sf-slack1 | <acomodi> For instance, instead of the S7MMCM module, you can use the S7PLL one from litex.soc.cores.clock | 15:59 |
| sf-slack1 | <acomodi> similarly as done for the arty board https://github.com/litex-hub/litex-boards/blob/9beaf25822c3794e14e8773778e014b3d7d9c80b/litex_boards/targets/arty.py#L42 | 15:59 |
| andrewb1999 | @acomodi: Thanks! I'll try that | 16:01 |
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| andrewb1999 | @acomodi: That fix worked, although sometimes the memtest from litex fails. I' | 19:32 |
| andrewb1999 | I'm on the nexys video so did you have to do anything special to get the DRAM to work reliably? | 19:33 |
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| sf-slack1 | <syed.ahmed.emails> Hi all, I'm not sure if I should ask this question here, so please let me know if there is some other channel which is more appropriate. I am seeing a VPR issue where placement fails with the following error: ``` BB estimate of min-dist (placement) wire length: 28852 Error 1: bb_cost_check: 113.861 and bb_cost: 108.685 differ in check_place. # Placement took 4.41 seconds (max_rss 294.0 MiB, delta_rss | 22:31 |
| sf-slack1 | +0.0 MiB) Incr Slack updates 145 in 0.0446406 sec Full Max Req/Worst Slack updates 128 in 0.00775294 sec Incr Max Req/Worst Slack updates 17 in 0.00117789 sec Incr Criticality updates 16 in 0.0066925 sec Full Criticality updates 129 in 0.0626554 sec Error 2: Type: Placement File: | 22:31 |
| sf-slack1 | /tmp/really-really-really-really-really-really-really-really-really-really-really-really-really-long-path/conda/conda-bld/symbiflow-vtr_1605895402114/work/vpr/src/place/place.cpp Line: 2469 Message: Completed placement consistency check, 1 errors found. Aborting program. ``` To give a little bit context, I'm working with @butta on his partial reconfig support for symbiflow. We are sythesizing some verilog on a PR region. | 22:31 |
| sf-slack1 | The test passes when we are using a different set of partition pins placement. So it's kinda hard to nail down what exactly is causing this. So I'm wondering if anybody has seen this error before and know a general direction I could look at. Any help is appreciated! | 22:31 |
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