Monday, 2020-08-10

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sf-slack<timo.callahan> @kgugala -- regarding https://github.com/antmicro-labs/tensorflow/tree/speech_zephyr/tensorflow/lite/micro/examples/micro_speech/zephyr_riscv -- do I need to add a special LiteX peripheral for the I2S?   Or not if it's just bitbanging?   Does the I2S PMod need to be on a particular slot on the Arty board?   Should I try to adapt what you have for I2C here --16:18
sf-slackhttps://github.com/timvideos/litex-buildenv/blob/master/targets/arty/tf.py?16:18
tpbTitle: tensorflow/tensorflow/lite/micro/examples/micro_speech/zephyr_riscv at speech_zephyr · antmicro-labs/tensorflow · GitHub (at github.com)16:18
tpbTitle: litex-buildenv/tf.py at master · timvideos/litex-buildenv · GitHub (at github.com)16:18
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sf-slack<kgugala> @timo.callahan the demo requires this IP https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/i2s.py16:21
tpbTitle: litex/i2s.py at master · enjoy-digital/litex · GitHub (at github.com)16:21
sf-slack<kgugala> and we were testing it with https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/16:21
tpbTitle: Pmod I2S2: Stereo Audio Input and Output - Digilent (at store.digilentinc.com)16:21
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sf-slack<timo.callahan> @kgugala thanks for the link!16:48
sf-slack<timo.callahan> @kgugala I've got the PMod already, excited to use it ...16:49
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andrewb1999Does anyone in here know about constant nets in 7 series?  I'm trying to define an ROI that covers multiple clock regions and I'm running into issues with being unable to route constant nets across the clock region boundary.20:11
andrewb1999I can provide more information is anyone is able to help20:11
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