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| -_whitenotifier-b- [vtr-verilog-to-routing] tpagarani opened issue #537: Analysis option in VTR does not generate Blackbox timing in SDF correctly - https://git.io/JJqLr | 07:41 | |
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| -_whitenotifier-b- [symbiflow-arch-defs] acomodi opened issue #1580: SRL tests fail if top outputs are connected to GND with new Yosys - https://git.io/JJqBj | 12:49 | |
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| -_whitenotifier-b- [prjxray] andrewb1999 opened issue #1388: SDF generation produces lowercase CELLTYPE for routing_bel in slicel/slicem - https://git.io/JJqay | 14:44 | |
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