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| FFY00 | litghost, are you talking to me? | 01:16 |
|---|---|---|
| FFY00 | that repo build nightly packages every day | 01:17 |
| FFY00 | what I am proposing is to notify the channel if for some reason any of them happens to fail | 01:18 |
| FFY00 | if one fails, the build is stopped | 01:18 |
| FFY00 | so you would get a max of one notification per day | 01:18 |
| HackerFoo | FFY00: Do you just use the latest commit for everything? That's going to break on anything that requires a coordinated update. | 01:36 |
| FFY00 | yes | 01:36 |
| FFY00 | there is no way around it | 01:37 |
| FFY00 | if it happens in the same day then there is no issue | 01:37 |
| HackerFoo | Why? Can't you specify the revision? | 01:37 |
| FFY00 | yes, but I won't be updating the revisions manually | 01:37 |
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| HackerFoo | This might not produce a useful set of packages as often as you'd hope. At least in my experience. | 01:43 |
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| FFY00 | well, yes | 02:29 |
| FFY00 | the that have releases are in the official repos | 02:30 |
| FFY00 | the others are just provided as is | 02:30 |
| FFY00 | I don't have time to be frequently updating the packages | 02:31 |
| FFY00 | and that would force me to keep track of what is happening in the upstream | 02:32 |
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| sky36 | Hey! struggling to get the symbiflow-examples running on my arty7_100t. The tests in symbiflow-arch-defs do have support. I presume there are problems in my environment. Unsure how to move over the built files for the arch-defs into the /opt/symbiflow/xc7/... directory in an appropriate manner to add support. | 12:23 |
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| sf-slack | <acomodi> Hi @sky36. Currently 100T is not yet supported in the symbiflow-examples. However, if you have built the 100T in arch-defs already, you could create a new directory under `/opt/symbiflow/.../share/symbiflow/arch/`. The files you would need to copy there are the following | 12:27 |
| sf-slack | <acomodi> arch.timing.xml rr_graph_xc7a100t_test.lookahead.bin rr_graph_xc7a100t_test.place_delay.bin rr_graph_xc7a100t_test.rr_graph.real.bin vpr_grid_map.csv | 12:27 |
| sf-slack | <acomodi> as well as the package-related directory containing the pinmap.csv file | 12:28 |
| sf-slack | <acomodi> Actually, this tar would contain the data necessary to have the 100T running | 12:29 |
| sf-slack | <acomodi> https://storage.googleapis.com/symbiflow-arch-defs/artifacts/prod/foss-fpga-tools/symbiflow-arch-defs/continuous/install/31/20200706-205356/symbiflow-arch-defs-install-6f9c6918.tar.xz | 12:29 |
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| sky36 | @acomodi - the typical format from the github instructions produces /share/arch/ rather than /share/symbiflow/arch/ | 13:07 |
| sky36 | Also, the github tar comes with the xray database | 13:07 |
| sky36 | I am attempting to move the files from the tar you provided into the older structure | 13:08 |
| sky36 | (I attempted to start fresh, and suffered errors with the 'pack' command | 13:08 |
| sf-slack | <acomodi> Yeah, there have been some changes in the install package which need to be integrated. This is a current work in progress. At the moment, it would be required to just move the files in the old structure as you did | 13:09 |
| sf-slack | <acomodi> what kind of errors are you seeing? | 13:09 |
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| sky36 | Currently yosys is telling me that it cannot load the xdc.so plugin | 13:21 |
| sky36 | when I attempt to build the counter example | 13:21 |
| sky36 | ERROR: Can't load module `./xdc': /opt/symbiflow/xc7/conda/envs/xc7/bin/../share/plugins/xdc.so: cannot open shared object file: No such file or directory | 13:21 |
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| sf-slack | <acomodi> Ok, there have been an update with the SymbiFlow/yosys version. I am experiencing the same issue with the latest conda package right now. To overcome this, you could set a specific yosys version which work (this needs to be done also for yosys-plugins. | 13:23 |
| sf-slack | <acomodi> GIve me a second to retrieve the correct versions | 13:23 |
| sky36 | more specifically: https://privatebin.net/?4781cfa6cec19953#5kFd7Qb7dbtZEqCKGYFgWSUZbL9HUaJMzbBwBenzvZF2 - thanks a lot! | 13:24 |
| tpb | Title: PrivateBin (at privatebin.net) | 13:24 |
| sf-slack | <acomodi> All right, so the conda package version of yosys would be `0.8_3925_g6bccd35a` . I see that the yosys-plugins already have pinned version, so no need to update that | 13:26 |
| sf-slack | <acomodi> The version needs to be added to the environment.yml file under `examples/xc7` | 13:26 |
| sky36 | excellent! - it seems to have gone further this time. Now I am suffering problems with vpr | 13:36 |
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| sky36 | https://privatebin.net/?547146b57c917085#4ATtmAR3GRPRSCWGftKpWunkgtGnhiLjNdsQjxgscfAV | 13:37 |
| tpb | Title: PrivateBin (at privatebin.net) | 13:37 |
| sky36 | Unsure whether I should use gdb to find the source of the segmentation fault | 13:37 |
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| sf-slack | <acomodi> Ah, right... forgot about that. The VPR version used in the current symbiflow-examples is out of date and compatible with the "old" install package. If you wish to use the newer architecture (100T) You would need to update also VTR (this will generate issues with the other devices though) | 13:39 |
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| sf-slack | <acomodi> `8.0.0.rc2_4003_g8980e4621` this version should work fine | 13:40 |
| sky36 | Ah - my next problem is unexpected arguments to the vpr command | 13:43 |
| sky36 | cd build && pack -e top.eblif -d xc7a100t_test -s /home/timothy/FPGA/SymbiFlow/symbiflow-examples/examples/xc7/counter_test/counter.sdcVPR FPGA Placement and Routing.Version: 8.1.0-dev+8980e4621Revision: v8.0.0.rc2-4003-g8980e4621Compiled: 2020-07-06T22:51:58Compiler: GNU 7.3.0 on Linux-4.15.0-1028-gcp x86_64Build Info: Release IPO | 13:43 |
| sky36 | VTR_ASSERT_LEVEL=2University of [email protected] is free open source code under MIT license.Unexpected command-line argument '--quick_check_route'usage: vpr architecture circuit [--pack] [--place] [--route] [--analysis] [--disp {on, off}] [--save_graphics {on, off}] [--graphics_commands | 13:43 |
| sky36 | GRAPHICS_COMMANDS] [-h] [--version] [--device DEVICE_NAME] [-j NUM_WORKERS] [--timing_analysis {on, off}] [--disable_errors DISABLE_ERRORS] [--suppress_warnings SUPPRESS_WARNINGS] [--route_chan_width CHANNEL_WIDTH] [OTHER_OPTIONS ...]make: *** [Makefile:23: build/top.net] Error 1 | 13:43 |
| sky36 | hm - there should be a nicer way to paste this | 13:44 |
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| sky36 | anyway, I've updated the bin folder to the one within the tar and am getting a Segfault again | 13:44 |
| sf-slack | <acomodi> That agument would need to be `--check_route quick` | 13:44 |
| sky36 | excellent, now place seems to be failing. | 13:46 |
| sky36 | Went into the bin folder and corrected the VPR options | 13:46 |
| sky36 | https://privatebin.net/?50c95939707d0daa#4rj7Dd5E9bTwrj49cwa8527jcG2yD1QPHa4h6Qq61JH3 | 13:47 |
| tpb | Title: PrivateBin (at privatebin.net) | 13:47 |
| sky36 | something is missing somewhere | 13:47 |
| TMM | hi all, I've been looking at the symbiflow-litex-linux example, but I can't actually get Linux to build. I'm trying to generate a new SoC with litex using their linux-on-litex repository but it doesn't really seem to have support for symbiflow, and a naive attempt to get it to use symbiflow (by changing how the board gets initialized) doesn't really work as there's a dependency on vivado hardcoded in one of the build scripts. This is my first | 13:47 |
| TMM | foray into anything symbiflow or FPGA to begin with so I'm kind of unsure where to start unraveling this. I'm getting some help on #litex also which I'm trying to use. I was kind of hoping that someone here maybe documented some of the steps they took? | 13:47 |
| sky36 | @acomodi I updated the prjxray folder to the latest version in the github, I get the ame error with the old and new versions | 13:48 |
| sf-slack | <acomodi> Ya, from the tarball linked you would need take the `prjxray_create_place_constraints` script and replace the one in the "old" install tar | 13:48 |
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| sky36 | Slowly making progress! had to also move over generate_constraints and edit the grid and pinmap paths to point to the right directories | 13:55 |
| sky36 | placing worked, now we're routing | 13:55 |
| sf-slack | <acomodi> Great, hopefully the installation step is going to be updated soon, so all these manual steps you have performed will not be required anymore to be able to build for the 100T devices as well | 13:56 |
| sky36 | I certainly hope so! - on the very last step right now | 13:57 |
| sky36 | bitstream is suiciding | 13:57 |
| sky36 | prjxray.fasm_assembler.FasmLookupError: Segment DB LIOB33, key LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY not found from line 'LIOB33_X0Y93.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY' | 13:57 |
| sf-slack | <acomodi> Ok, one last step, you would need to update the database with the most recent one | 13:58 |
| sky36 | Yep - I cloned the pjxray from github | 13:58 |
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| sf-slack | <acomodi> Ok, so from the `prjxray/database` dir grab the artix7 directory and replace the one under `symbiflow/xc7/install/share/prjxray/prjxray-db` | 14:02 |
| -_whitenotifier-b- [symbiflow-arch-defs] acomodi opened issue #1578: Remove `test` from full-devices that are packed in the install tarball - https://git.io/JJtCp | 14:05 | |
| sky36 | yep - cd build && write_bitstream -d artix7 -f top.fasm -p xc7a100tcsg324-1 -b top.bitWriting bitstream ...Traceback (most recent call last): File "/opt/symbiflow/xc7/install/bin/python/prjxray/utils/fasm2frames.py", line 306, in <module> main() File "/opt/symbiflow/xc7/install/bin/python/prjxray/utils/fasm2frames.py", line 294, in main | 14:06 |
| sky36 | run( File "/opt/symbiflow/xc7/install/bin/python/prjxray/utils/fasm2frames.py", line 199, in run raise fasm_assembler.FasmLookupError('\n'.join(missing_features))prjxray.fasm_assembler.FasmLookupError: Segment DB LIOB33, key LIOB33.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY not found from line | 14:06 |
| sky36 | 'LIOB33_X0Y93.IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18_LVCMOS25_LVCMOS33_LVTTL_SSTL135.IN_ONLY'make: *** [Makefile:35: build/top.bit] Error 1``` | 14:06 |
| sky36 | oh dear - how do I paste code? | 14:06 |
| sky36 | same issue | 14:06 |
| sky36 | pjxray-db is correctly updated, with the old version it doesnt see "xc7a100tcsg324" at all | 14:06 |
| sf-slack | <acomodi> Hmmm, probably then is the other way around, Try to get the older version of the db (the one found in the original install tarball) and grab the xc7a100tcsg324 from the new one | 14:10 |
| sky36 | https://privatebin.net/?99c696215ce8376a#Fu7uEBeC2HqeG3QE6xC4pcC5cHQAXuFye4YfcRbpNGSr | 14:12 |
| tpb | Title: PrivateBin (at privatebin.net) | 14:12 |
| sky36 | its caught on fire :D | 14:13 |
| sky36 | even more lookup errors - hmmm | 14:13 |
| sf-slack | <acomodi> Aha, got it, it is actually a fasm2frames issue. I was wrong. The updated version of the db was all right | 14:14 |
| sf-slack | <acomodi> You would need to replace the fasm2frames script from the prjxray updated repo (prjxray/utils/fasm2frames.py) to the /bin/python/ dir | 14:15 |
| sky36 | hmm interesting... | 14:17 |
| sky36 | cool! got the bitstream file | 14:21 |
| sf-slack | <acomodi> Nice! | 14:21 |
| sky36 | Does symbiflow have a tool to flash it - or | 14:21 |
| sf-slack | <acomodi> You can use `xc3sprog` | 14:22 |
| sf-slack | <acomodi> xc3sprog -c nexys4 <bitstream-name>.bit | 14:23 |
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| sf-slack | <acomodi> http://xc3sprog.sourceforge.net/ | 14:24 |
| tpb | Title: xc3sprog (at xc3sprog.sourceforge.net) | 14:24 |
| sky36 | Acomodi - thank you very much | 14:36 |
| sky36 | really appreciate it - it would've taken me days to figure this out on my own | 14:36 |
| sky36 | can finally have a better, more streamlined workflow without using the nasty vivado cringe suite | 14:37 |
| sky36 | Do you have any idea of timescale of when the 100t will be added to the examples? | 14:51 |
| sf-slack | <acomodi> @sky36 No problem ;) Regarding the timescale, there are a couple of things to get fixed. Probably it is in the order of days, worst case a few weeks. | 15:06 |
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| sky36 | Amazing, i'm very optimistic. Thanks to everyone for a lot of the hard work that's gone into this - I didn't believe an open source toolchain existed when I first heard about it! | 15:27 |
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| litghost | TMM: Which instructions were you following? | 15:49 |
| litghost | TMM: There is a A50T LiteX linux example in https://github.com/SymbiFlow/symbiflow-examples/tree/master/examples/xc7/linux_litex_demo | 15:49 |
| tpb | Title: symbiflow-examples/examples/xc7/linux_litex_demo at master · SymbiFlow/symbiflow-examples · GitHub (at github.com) | 15:49 |
| TMM | litghost: it doesn't actually use litex but has a prebuild verilog output generated by litex | 16:57 |
| litghost | TMM: There are some outstanding issues around consuming the output of LiteX directly that we are working on. Some have open PR's, and some are in active development | 16:59 |
| litghost | TMM: I can see if I can find the notes about the outstanding changes between the LiteX output and something that works | 16:59 |
| TMM | litghost: ok, that would be great because the example isn't entirely complete either. The json file to describe the images is missing, and lxterm only runs at 115200 at most. So there's some issues with the example even. Or I did something incredibly dumb. I have to admit that this is the first thing I've ever done with an FPGA at all. I'm trying to work out how all of this fits together, it's a little daunting at first. | 17:00 |
| litghost | TMM: Absolutely. We are actively trying to burn down issues that prevent the LiteX output from working directly with the toolchain. | 17:01 |
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| litghost | TMM: We actually have an issue tracking what you are describing here: https://github.com/SymbiFlow/symbiflow-examples/issues/12 Work to support that issue is on going | 17:04 |
| sf-slack | <acomodi> TMM: FYI, there is the possiblity to load the Linux images also with ethernet. (There is a wiki describing how to setup the net interface https://github.com/timvideos/litex-buildenv/wiki/Networking). One thing to notice is that the UDP port would need to be set to 69 instead of 6069. Using ethernet is much faster than the 115200 baud rate with lxterm | 17:06 |
| tpb | Title: Networking · timvideos/litex-buildenv Wiki · GitHub (at github.com) | 17:06 |
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| TMM | sf-slack: right, to see it working that would be nice! But I kind of need to be able to generate my own socs :) What I'm planning to do requires me to add some opcodes to the cpu :) | 17:30 |
| andrewb1999 | kgugala / acomodi: I've been talking to mitho about instability in the prjxray-db sdf generation and was wondering if you could take a look at fixing this. I needed to make changes to prjxray-db to get some of my work merged, but now the new database generated runs into sdf issues in arch-defs CI. Not being able to get a new database merged into arch-defs is holding back merging a lot of my other work. | 18:13 |
| sf-slack | <kgugala> andrewb1999: can you link a PR with unstable sdf? | 18:18 |
| andrewb1999 | kgugala: https://github.com/SymbiFlow/symbiflow-arch-defs/pull/1571 | 18:30 |
| tpb | Title: build(deps): bump third_party/prjxray-db from `20adf09` to `e45604d` by dependabot-preview · Pull Request #1571 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 18:30 |
| andrewb1999 | kgugala: And here are the changes in the db generation https://github.com/SymbiFlow/prjxray-db/commit/e45604d941615d6eef722f61fe857b6688088b6b | 18:31 |
| HackerFoo | litghost: Does this make sense? https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/1205#issuecomment-655048936 | 18:39 |
| tpb | Title: A New Simulated Annealing Schedule by HackerFoo · Pull Request #1205 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 18:39 |
| litghost | HackerFoo: I don't think I disagree at a high level. It would be good to get a rational from the VTR devs for why QoR improvements are flagged. Do you remember if we directly resolved that question? | 18:41 |
| HackerFoo | I don't think it has been resolved, but I can see why they would want to know if e.g. CPD went down to something physically impossible. | 18:44 |
| HackerFoo | So it probably makes sense to just adjust the lower limits. | 18:44 |
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| TMM | litghost: is there anything someone who's main claim to fpga fame is some blinking leds can do to help with this? | 19:17 |
| litghost | TMM: Sorry, can rephrase your question? I'm not certain I understood you. | 19:22 |
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| TMM | litghost: you said there were a bunch of things still being worked on. I just wondered if someone with very limited experience can do anything useful there. | 19:27 |
| litghost | TMM: Absolutely. Do you have experience with C++ or python? If not, simply updating the documentation for the symbiflow-example could be useful right now. Give me a minute while I look over our burndown list | 19:30 |
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| TMM | litghost: yeah, I write C++ for the Godot game engine, it's my job now. :) | 19:45 |
| HackerFoo | TMM: Nice | 19:45 |
| TMM | HackerFoo: thanks! :D | 19:47 |
| litghost | TMM: So something we want to do is propagate clocking constraints through yosys transformations. In particular, yosys adds IBUF and BUFG's as part of it's passes. So an inpad named "clk" is still "clk" before the IBUF, but after the IBUF is named something like "\$iopadmap.clk", etc. I believe LiteX relies on simply constraining the inpad "clk" in it's xdc | 19:49 |
| litghost | TMM: We want something to propigate input clock constraints from the xdc to follow yosys transformations where the relevant net is split, so that when it comes time to run the design into VPR, the constraints are supplied on the new nets | 19:50 |
| litghost | TMM: We've handled this to date by modifying LiteX's clock constraints to match any transformed net names | 19:51 |
| litghost | TMM: We have an initial xdc plugin here: https://github.com/SymbiFlow/yosys-symbiflow-plugins/blob/master/xdc-plugin/xdc.cc, but right now it is only annotating IO directives onto cells, not anything wr.t. create clocks | 19:52 |
| litghost | TMM: We have an initial issue about this here: https://github.com/SymbiFlow/symbiflow-arch-defs/issues/1352 | 19:53 |
| tpb | Title: Clock propagation story · Issue #1352 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 19:53 |
| litghost | TMM: There is also a need to have something propigate clock constraints from the input of the PLL/MMCM to the output of the PLL/MMCM | 19:54 |
| TMM | OK, this is a little over my head but it feels maybe not too far over my head. Parsers and compilers are a hobby of mine so I think once I understand the problem a bit better I can probably fix it. I'll try to understand what some of the terms mean and go through the yosys code. Also: TCL gross ;) | 19:55 |
| litghost | TMM: TCL is super gross, but it is what we got :( | 19:56 |
| TMM | Is there a minimal problem verilog file that should synthesize but doesn't due to this? | 19:57 |
| litghost | TMM: Any design that leaves off the IBUF and BUFG when synthesized with yosys will have the new nets | 19:58 |
| TMM | Right, but so far all I've done is blink some LEDs :) I'll first learn enough verilog to encounter the problem then | 19:59 |
| litghost | TMM: So blinking some LEDs will manifest this issue, if you tried to constrain the clock | 19:59 |
| litghost | TMM: However blinky is typically simple enough that clock constraints are not required | 20:00 |
| litghost | TMM: However designs like LiteX have tighter (and weirder) timing constraints than something like blinky | 20:00 |
| TMM | Imagine that! :D | 20:01 |
| litghost | TMM: As an example, take https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc/xc7/tests/counter/counter_basys3.v (which is a blinky). In this case the design has an explict BUFG, but an implicit IBUF | 20:01 |
| tpb | Title: symbiflow-arch-defs/counter_basys3.v at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 20:01 |
| litghost | TMM: Post-synthesis, yosys will insert a IBUF between the input "clk" and create a new net after the IBUF | 20:02 |
| litghost | TMM: In designs without the explicit BUFG, there will be a similar insertion between the net from the IBUF and the output for the BUFG | 20:02 |
| TMM | OK, I think I see. So this problem would manifest itself in the yosys json files, right? | 20:04 |
| litghost | TMM: Sort of. To be clear, the issue is communicating the constraints from the input XDC/SDC file down to VPR | 20:05 |
| litghost | TMM: VPR sees 3 clock nets (the pad net, the net that is the output of the IBUF, and the net that is the output of the BUFG) | 20:05 |
| litghost | TMM: By default, none of these nets will be constrained | 20:06 |
| litghost | TMM: If the input SDC is passed directly to VPR, only that first net (the pad to the IBUF input) will be constrained | 20:06 |
| litghost | TMM: However the "right" behavior is to have a clock tree that originates at the IBUF, propigates through the IBUF, through the BUFG, etc | 20:07 |
| litghost | TMM: MMCM/PLL propigation is also highly valuable, as ideally for static MMCM/PLL configuration, the tooling would be able to generate the correct constraints on both the input to the PLL, and the output | 20:08 |
| TMM | OK, so, I maybe got this entirely wrong but: Yosys generates a new wire between the bufg and whatever comes after it. Instead this wire shouldn't be there but be connected to the input clock pad? | 20:10 |
| litghost | TMM: Yosys's behavior is correct, we want that BUFG. It is actually very important that it be there. | 20:11 |
| TMM | I'm trying! Thanks for your patience. | 20:12 |
| litghost | TMM: What we need to do is take the initial SDC (constraint the input pad), and have it accurately reflect the final clock tree going into place and route | 20:12 |
| TMM | Is it OK if I type out my current understanding? Because I don't see how these constraints fit in | 20:18 |
| litghost | Sure | 20:26 |
| TMM | OK, so, the sdc file in the case of the counter describes says that the maximum clock propagation delay is 10ns. So this means that no set of gates as a whole can take longer than 10ns to propagate the clock and do whatever logic they were going to do. Correct? | 20:35 |
| TMM | I'm talking about `create_clock -period 10 bufg` | 20:35 |
| TMM | What yosys does is generate a gate-level description of the circuit described in the verilog file. but it can't know about these physical delays, right? | 20:38 |
| TMM | That would be up to the routing and placement tool, to fit the gates that yosys generated into the actual physical gates of the chip. | 20:38 |
| TMM | And whether or not that 10ns clock propagation can be achieved can't be known until then, right? | 20:39 |
| litghost | TMM: More specifically, yosys is working at a different abstration level than the P&R tool, and cannot do precise clock constraining. Some physical synthesis is done, but I don't believe it is constraint driven today | 20:39 |
| litghost | TMM: Adding more physical synthesis is future work | 20:39 |
| TMM | I'm not arguing :) I'm trying to put to words the way I think this is supposed to work | 20:40 |
| litghost | TMM: But it is correct that the P&R tool has a more complete and precise model of the underlying hardware. | 20:40 |
| litghost | TMM: This is a little tangent to the actually need. The need to is express the clocking constraints on the nets downstream of the buffering clock objects (e.g. the IBUF and the BUFG, and/or PLL/MMCM). | 20:41 |
| TMM | Because I'm not entirely sure what yosys can do with the clock contraint information, so I guess I'm not sure what exactly should happen. Is the constraint encoded as a sort of metadata in the RTL? If so is what needs to happen that the clock constraint 'simply' (I'm assuming it's not that simple) needs to be tracked so that the RTL contains the whole chain up from clk to bufg (and the implicint IBUF)? So that the R&P tool can know that all | 20:42 |
| TMM | those components share that 10ns constraint | 20:42 |
| litghost | TMM: The P&R tool uses the input clock constraints to drive the optimization to meet the constraint. If the constraint is absent or missing, then the optimization will focus on the wrong parts | 20:42 |
| litghost | TMM: The goal is to take a clock constraint on the pad (e.g. "input clk") and propigate those constraints to the downstream nets, so that the P&R tool does the right thing | 20:43 |
| TMM | right, and the P&R tool (in the case of counter) needs to know that the clk and bufg wires should be counted together to meet the 10ns constraint? So if bufg takes 1ns, it should be able to know that the implicit ibuf now has 9ns left? | 20:44 |
| litghost | TMM: > So if bufg takes 1ns, it should be able to know that the implicit ibuf now has 9ns left? | 20:44 |
| litghost | TMM: That's not quiet right | 20:44 |
| litghost | TMM: The IBUF or BUFG actually create a relationship between the input and the output | 20:44 |
| litghost | TMM: So it isn't a direct subtraction | 20:44 |
| litghost | TMM: However as a first cut, the relationship can be assumed to be 0 delay, as a first cut | 20:45 |
| litghost | TMM: The reality is more complicated, but that is something that can be added later | 20:45 |
| litghost | TMM: The precise description of the BUFG input to output relationship is that the BUFG adds some delay and some jitter/variance | 20:45 |
| litghost | TMM: However most clocked elements in the design should be downstream of the BUFG, so the delay through the BUFG is immaterial | 20:46 |
| litghost | TMM: Only in the case where a piece of logic is capturing an edge that was launched from the other side of a buffer would the delay through the buffer factor in | 20:47 |
| litghost | TMM: For now, simply propigating the relationship as 0 delay and 0 jitter through the IBUF and BUFG is a good first approximation, with TBD constants to factor in the true pre- post- buffer delays | 20:48 |
| TMM | I guess maybe I'm not 100% clear on what 'propagating through' means exactly. Is that metadata for P&R? Or does it actually change the netlist from yosys? | 20:49 |
| litghost | TMM: The netlist does not change. The constraints should change, and/or be added too | 20:49 |
| litghost | TMM: So a constraint on just the input pad, becomes the input pad, the IBUF output and the BUFG output. In the case of a clock generation element, there is a relationship between the PLL input and output (e.g. phase shift and/or frequency change) | 20:50 |
| litghost | TMM: So as an example, the user says "create_clock -period 10 clk", which is then propigated to a net "clk_bufg". In that case, a new constraint can be added simply as "create_clock -period 10 clk_bufg" | 20:53 |
| litghost | TMM: If there is a delay though the element, then the propigated constraint would something like "create_clock -waveform {1 6} clk_bufg" (for a 1 ns delay through the element) | 20:54 |
| TMM | oh, so the work should generate a new sdc file? | 20:55 |
| litghost | TMM: Yes | 20:55 |
| litghost | TMM: VPR SDC also supports clock uncertainity (e.g. jitter) via "set_clock_uncertainty" | 20:55 |
| litghost | TMM: The SDC input format to VPR supports expressing both delay through clocking elements and jitter through elements, but we don't have something that takes a fully elaborated netlist from yosys and just an input pad constraint, and creating the "full" constraint description for the clock network | 20:56 |
| TMM | ah, ok, that part I really didn't understand. So should this be a tool that runs separately from yosys that takes the json file and does this analysis or should yosys spit out an sdc file as well as the various other files? | 20:57 |
| TMM | And I guess I don't fully understand how something at that level can know how much delay and jitter there is going to be. Isn't that dependent on the actual silicon? | 20:58 |
| TMM | And I presume the clock integrity related to the speed? | 20:58 |
| litghost | TMM: It is dependent on the silicon. The initial tool though can just propigate assuming 0 delay / 0 jitter as a first step | 20:59 |
| litghost | TMM: As for whether this lives outside of yosys or inside as a plugin or yosys script is part of the work | 21:01 |
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| litghost | TMM: We have an XDC plugin that we were thinking could be used to capture the clock constraints from the XDC input, but that is not currently wired to create even a simple XDC -> SDC passthrough | 21:02 |
| TMM | OK, not knowing any of the workings of yosys, on the face of it it seems that just a verilog parser should be able to figure this out, but I guess you'd have to know what names yosys is going to use to generate the sdc file | 21:02 |
| zyp | so to put it simply, yosys is transforming the nets so that the constraints for the input doesn't match the names in the output, so the constraints also needs to be transformed to match? | 21:02 |
| litghost | zyp: It isn't always just a name transformation, somethings it is a duplicate and rename. That is what I've been meaning by "propigate" | 21:03 |
| litghost | zyp: But your gist is pretty close | 21:04 |
| TMM | OK, I guess I have some idea on what needs to happen. I'll take a stab at understanding what yosys does exactly and if there's some output formats or logs I can use to understand what's happening | 21:05 |
| litghost | TMM: After yosys is done with synthesis, the netlist can be described in any number of formats, e.g. json, eblif, edif, verilog | 21:05 |
| TMM | OK, I will do my best! Thanks a lot for your time. I think I have enough to at least come back with more clever questions later :) | 21:08 |
| TMM | And, thanks for working on this. I have been interested in working on fpgas forever but I've never had any interest in using a non-free tool to do it | 21:09 |
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| litghost | TMM: Have a fun time, this stuff is pretty cool. I believe trying to figure this out is actually a good entry point | 21:10 |
| zyp | TMM, absolutely agree on that last point :) | 21:10 |
| zyp | I bought my first fpga devboard 13 years ago, and I'm still a FPGA novice, since the tools have been putting me off every time I've tried doing anything | 21:11 |
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