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| mithro | New symbiflow target :-P -- https://twitter.com/enjoy_digital/status/1275488066011004928 | 01:27 |
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| andrewb1999 | litghost/mithro: When creating my own synth IOs everything runs through generating the patched.bin, but then when generating the real.bin VPR prints out millions of warnings about no routing path and then crashes on a negative criticality error. | 02:15 |
| andrewb1999 | Any advice on why creating synth IOs at places other than VBRKs would cause this issue? I belive that's the only thing I am changing | 02:17 |
| andrewb1999 | If not, i'll get more info and post an issue | 02:17 |
| litghost | More info is needed | 02:17 |
| litghost | I suspect your graph limit and used wires are the likely problems | 02:17 |
| litghost | Negative criticality indicates a timing issue, which should be investigated | 02:18 |
| andrewb1999 | Ok I'll get more info and post an issue. In a more general question, what limitation is there on what wires can be used for synth IOs relative to the graph limit? | 02:19 |
| andrewb1999 | Is it just that they have to touch to boundary? | 02:19 |
| -_whitenotifier-f- [symbiflow-arch-defs] tcal-x opened issue #1546: fasm2bels: max recursion depth exceeded, make_routes.py, xc7a100t, soc/litex/base - https://git.io/JfplC | 02:21 | |
| daniellimws | mithro: What do you mean by status? | 02:25 |
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| mithro | daniellimws: The packages are in a state of flux around naming | 02:46 |
| daniellimws | mithro: which ones? | 02:47 |
| mithro | http://j.mp/edda-status & bit.ly/edda-conda-eda-spec -- I think | 02:51 |
| tpb | Title: EDDA Package Status (EDA Tools Conda Packages) - j.mp/edda-status - Google Sheets (at j.mp) | 02:51 |
| daniellimws | mithro: You mean unstandardized namings? | 02:56 |
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| mithro | daniellimws: I think yosys package is becoming the upstream git yosys and symbiflow-yosys package becoming https://github.com/SymiFlow/yosys | 03:04 |
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| mithro | and eventually the patches to SymbiFlow/yosys should be going away.... | 03:07 |
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| mithro | @daniellimws: But I don't know the current status of the migration -- kgugla might know | 03:09 |
| daniellimws | oh ok | 03:11 |
| mithro | @daniellimws -- I think we should also investigate using whitequark's Yosys in WASM package too | 03:11 |
| -_whitenotifier-f- [sphinxcontrib-verilog-diagrams] mithro opened issue #40: Investigate if we can use the Yosys uploaded to PyPi - https://git.io/Jfp8N | 03:14 | |
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| daniellimws | Can't seem to find any examples in the repo | 03:20 |
| mithro | daniellimws: Of? | 03:21 |
| daniellimws | How to use nmigen_yosys | 03:21 |
| mithro | daniellimws: Your too quick - I hadn't finished adding more links | 03:23 |
| mithro | https://github.com/SymbiFlow/sphinxcontrib-verilog-diagrams/issues/40 | 03:23 |
| tpb | Title: Investigate if we can use the Yosys uploaded to PyPi · Issue #40 · SymbiFlow/sphinxcontrib-verilog-diagrams · GitHub (at github.com) | 03:23 |
| mithro | daniellimws: https://yowasp.github.io/ | 03:25 |
| tpb | Title: YoWASP | Unofficial WebAssembly-based packages for Yosys, nextpnr, and more (at yowasp.github.io) | 03:25 |
| mithro | daniellimws: Might also be worth asking whitequark in #nmigen | 03:25 |
| daniellimws | Ah ok | 03:27 |
| mithro | daniellimws: Also yowasp was also only released today -- so :-) | 03:27 |
| daniellimws | Looks really cool | 03:27 |
| mithro | daniellimws: Did you see https://github.com/SymbiFlow/sphinxcontrib-verilog-diagrams/issues/36 ? | 03:54 |
| tpb | Title: With no-license should have a way to display the skipped output · Issue #36 · SymbiFlow/sphinxcontrib-verilog-diagrams · GitHub (at github.com) | 03:54 |
| daniellimws | mithro: Yup saw it but feels like gonna be troublesome to implement :P Need to make sure it also works well with other themes? | 03:56 |
| daniellimws | At least the default theme | 03:56 |
| mithro | @daniellimws -- There are only 2 that I care about - The symbiflow material design one and the default readthedocs one | 03:56 |
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| daniellimws | Alright I'll give it a try these few days | 03:57 |
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| tnt | kgugala: If I instanciate a logic_cell_macro , will it actually implement it ? | 10:35 |
| sf-slack3 | <kgugala> yesterday, techmap for that was merged | 10:35 |
| sf-slack3 | <kgugala> so now you should be able to instantiate logic_cell_macro | 10:36 |
| tnt | Oh, great :) | 10:38 |
| tnt | And gclk fixes too it seems. | 10:45 |
| sf-slack3 | <kgugala> yep | 10:45 |
| sf-slack3 | <kgugala> there is still some stuff to be done in gclk | 10:46 |
| sf-slack3 | <kgugala> I think it should be ready today | 10:46 |
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| tnt | kgugala: https://pastebin.com/raw/MjbLz0eJ Does that ring a bell ? | 11:11 |
| sf-slack3 | <kgugala> nope, can you file an issue about it | 11:12 |
| tnt | done aa65abdeb8754f60f425ca4ecfa03c176104e90f | 11:14 |
| tnt | err, I meant https://github.com/QuickLogic-Corp/symbiflow-arch-defs/issues/29 | 11:14 |
| tpb | Title: "TypeError: list indices must be integers or slices, not str" in timing importer · Issue #29 · QuickLogic-Corp/symbiflow-arch-defs · GitHub (at github.com) | 11:14 |
| sf-slack3 | <kgugala> I'll take a look on that | 11:14 |
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| sf-slack3 | <c-slack> How would I approach a frontend for a new chip? How easy is it to port the fuzzer? More specifically I'd like to try to adapt the ECP5 fuzzer to the MachXO3. | 13:21 |
| Lofty | daveshah: ^ | 13:21 |
| daveshah | talk to cr1901 as he is working on MachXO2 which is very similar | 13:21 |
| daveshah | I don't know if he is on this channel, but he is probably on ##openfpga or #yosys | 13:21 |
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| sf-slack3 | <c-slack> thanks! | 13:29 |
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| tnt | Anyone know how to constrain cross clock parth in VPR ? | 15:32 |
| tnt | ATM it basically constraint them to ... 0ns ... which obviously fails. I'd jue like to set some max delay spec. | 15:32 |
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| tnt | set_max_delay 40 -from [get_clocks {clk_wb}] -to [get_clocks {clk_usb}] | 15:55 |
| tnt | => Message: set_max_path must specify at least one -from or -to clock | 15:55 |
| tnt | No-one ever used that ? | 16:12 |
| tnt | I have "create_clock -period 83.00 clk_wb" and it finds the clokc for that just fine so I have no clue wtf it's complainaing about for the max delay. | 16:13 |
| tnt | Ok, so ... if I use "usb_I.uc_clk" it works :/ .... but I don't _control_ that name, it's whatever yosys decided to use. | 16:15 |
| tnt | And the eblif has a ".names usb_I.uc_clk clk_wb" marking them as being the same. | 16:16 |
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| litghost | So we had some issues around this | 17:13 |
| litghost | But I believe that all clock aliases are supported, if they are present in the eblif | 17:13 |
| litghost | We have an open issue about propigating clock constraints through yosys transformations, but it hasn't been finished yet | 17:14 |
| litghost | Which git hash is your VTR at? | 17:14 |
| litghost | Because I believe upstream VTR and symbiflow VTR both support using an aliased net name in SDC | 17:15 |
| litghost | tnt: The relevant code was added in https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/1173 | 17:18 |
| tpb | Title: vpr: use alias name mapping for clock nets when removing buffer luts by acomodi · Pull Request #1173 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 17:18 |
| tnt | litghost: The alias works for 'create_clock' (to set up period/frequency). But not for set_max_path :/ | 17:23 |
| tnt | hash is 8980e46218542888fac879961b13aa7b0fba8432 | 17:23 |
| litghost | tnt: Totally possible. Should be an easier enough fix | 17:23 |
| litghost | tnt: Can you describe the clock relationship between clk_wb and clk_usb? | 17:25 |
| litghost | tnt: Are they simply phase shifted from one another? | 17:25 |
| litghost | tnt: You should definitely fill an issue on VTR about set_max_delay not support net aliases, I think that was an oversight | 17:27 |
| litghost | tnt: However depending on the clock relationship you are trying to describe, I believe create_clock is enough | 17:27 |
| -_whitenotifier-f- [sphinxcontrib-verilog-diagrams] mithro opened issue #41: Weird formatting - https://git.io/Jfhvj | 17:28 | |
| tnt | litghost: they are different frequencies (12M and 36M). | 17:30 |
| tnt | But there is proper CDC for all signals not assuming any relationship, so to make sure it works, it just needs to make sure the max delay is shorter than 1 clock period of the slower clock. | 17:30 |
| tnt | (and definitely doesn't work without constrain ... by default it tries to capture at edge 0 ns the data emitted at edge 0 ns ... which obviously yields a violation). | 17:32 |
| litghost | tnt: You have reached the edge of my limited knowledge on timing enforcement. kmurray from the VTR project should be able to answer your question. | 17:32 |
| litghost | tnt: I believe in your case, the fact that set_max_delay isn't respecting the clock alias is a straight forward bug, and should be fixed | 17:33 |
| litghost | tnt: Does the analysis work as expected if you use the other net alias? | 17:33 |
| tnt | yup, I used usb_I.uc_clk in the constraint temporarily and it works as expected. | 17:34 |
| litghost | tnt: Ok, thats good. Then it sounds like the solution is to add net alias support to https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vpr/src/timing/read_sdc.cpp#L896 | 17:35 |
| tpb | Title: vtr-verilog-to-routing/read_sdc.cpp at master · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 17:35 |
| litghost | tnt: I expect it should be a straight forward change. If you don't feel comfortable making the change, ping acomodi, as they made the previous fix around this issue | 17:35 |
| -_whitenotifier-f- [vtr-verilog-to-routing] smunaut opened issue #524: Net alias not properly considered when creating set_{min,max}_delay constrainst - https://git.io/JfhfQ | 17:43 | |
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| HackerFoo | In case anyone else sees this bug: https://github.com/YosysHQ/yosys/issues/2190 | 21:47 |
| tpb | Title: Stack overflow in XAigerWriter::bit2aig(Yosys::RTLIL::SigBit) · Issue #2190 · YosysHQ/yosys · GitHub (at github.com) | 21:47 |
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| -_whitenotifier-f- [python-symbiflow-v2x] mithro opened issue #68: Publish to PyPi - https://git.io/JfhZz | 22:27 | |
| -_whitenotifier-f- [fpga-tool-perf] HackerFoo opened issue #172: write_bitstream fails on baselitex with nextpnr-xilinx and latest yosys - https://git.io/JfhZ6 | 22:34 | |
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